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1. 发明申请

US20120178237A1 DEEP WELL STRUCTURES WITH SINGLE DEPTH SHALLOW TRENCH ISOLATION REGIONS 有权
标题翻译：深深的结构与单深深浅的分离分离区域
公开(公告)号：US20120178237A1
公开(公告)日：2012-07-12
申请号：US13418994
申请日：2012-03-13
申请人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
发明人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/0921
摘要： A method of forming a semiconductor device includes defining a first type region and a second type region in a substrate, t separated by one or more inter-well STI structures; etching and filling, in at least one of the first type region and the second type region, one or more intra-well STI structures for isolating semiconductor devices formed within a same polarity well, wherein the one or more inter-well STI structures are formed at a substantially same depth with respect to the one or more intra-well STI structures; implanting, a main well region, wherein a bottom of the main well region is disposed above a bottom of the one or more inter-well and intra-well STI features; and implanting, one or more deep well regions that couple main well regions, wherein the one or more deep well regions are spaced away from the one or more inter-well STI structures.
摘要翻译：一种形成半导体器件的方法包括：在衬底中限定由一个或多个阱间STI结构分离的第一类型区域和第二类型区域; 蚀刻和填充在第一类型区域和第二类型区域中的至少一个区域中的一个或多个井下STI结构，用于隔离在相同极性阱内形成的半导体器件，其中形成一个或多个阱间STI结构相对于一个或多个井内STI结构基本相同的深度; 植入，主井区，其中主井区的底部设置在所述一个或多个井间和井内STI特征的底部之上; 以及植入，连接主井区域的一个或多个深井区域，其中所述一个或多个深井区域与所述一个或多个井间STI结构间隔开。

2. 发明授权

US08846486B2 Deep well structures with single depth shallow trench isolation regions 有权
标题翻译：深井结构，具有单深度浅沟槽隔离区
公开(公告)号：US08846486B2
公开(公告)日：2014-09-30
申请号：US13418994
申请日：2012-03-13
申请人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
发明人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
IPC分类号： H01L21/761 , H01L21/8238 , H01L21/762 , H01L27/092
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/0921
摘要： A method of forming a semiconductor device includes defining a first type region and a second type region in a substrate, t separated by one or more inter-well STI structures; etching and filling, in at least one of the first type region and the second type region, one or more intra-well STI structures for isolating semiconductor devices formed within a same polarity well, wherein the one or more inter-well STI structures are formed at a substantially same depth with respect to the one or more intra-well STI structures; implanting, a main well region, wherein a bottom of the main well region is disposed above a bottom of the one or more inter-well and intra-well STI features; and implanting, one or more deep well regions that couple main well regions, wherein the one or more deep well regions are spaced away from the one or more inter-well STI structures.
摘要翻译：一种形成半导体器件的方法包括：在衬底中限定由一个或多个阱间STI结构分离的第一类型区域和第二类型区域; 蚀刻和填充在第一类型区域和第二类型区域中的至少一个区域中的一个或多个井下STI结构，用于隔离在相同极性阱内形成的半导体器件，其中形成一个或多个阱间STI结构相对于一个或多个井内STI结构基本相同的深度; 植入，主井区，其中主井区的底部设置在所述一个或多个井间和井内STI特征的底部之上; 以及植入，连接主井区域的一个或多个深井区域，其中所述一个或多个深井区域与所述一个或多个井间STI结构间隔开。

3. 发明授权

US08198700B2 Deep well structures with single depth shallow trench isolation regions 有权
标题翻译：深井结构，具有单深度浅沟槽隔离区
公开(公告)号：US08198700B2
公开(公告)日：2012-06-12
申请号：US12691196
申请日：2010-01-21
申请人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
发明人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
IPC分类号： H01L27/092
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/0921
摘要： A semiconductor device structure includes a first type region and a second type region defined in a substrate, the first type region and second type region separated by one or more inter-well shallow trench isolation (STI) structures. At least one of the first type region and the second type region has one or more intra-well STI structures formed therein for isolating semiconductor devices formed within a same polarity well. The inter-well STI structures are formed at a substantially same depth with respect to the intra-well STI structures. A main well region is formed such that a bottom of the main well region is disposed above a bottom of the inter-well and intra-well STI features. One or more deep well regions couple the main well regions otherwise isolated by the intra-well STI structures, wherein the deep well regions are spaced away from the inter-well STI structures.
摘要翻译：半导体器件结构包括限定在衬底中的第一类型区域和第二类型区域，第一类型区域和第二类型区域被一个或多个阱间浅沟槽隔离（STI）结构隔开。第一类型区域和第二类型区域中的至少一个具有形成在其中的一个或多个井内STI结构，用于隔离在相同极性内形成的半导体器件。井间STI结构相对于井内STI结构形成在基本相同的深度。形成主阱区域，使得主阱区域的底部设置在井间和井内STI特征的底部之上。一个或多个深井区域连接主井区域，否则由井内STI结构隔离，其中深井区域与井间STI结构间隔开。

4. 发明申请

US20110175190A1 DEEP WELL STRUCTURES WITH SINGLE DEPTH SHALLOW TRENCH ISOLATION REGIONS 有权
标题翻译：深深的结构与单深深浅的分离分离区域
公开(公告)号：US20110175190A1
公开(公告)日：2011-07-21
申请号：US12691196
申请日：2010-01-21
申请人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
发明人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/0921
摘要： A semiconductor device structure includes a first type region and a second type region defined in a substrate, the first type region and second type region separated by one or more inter-well shallow trench isolation (STI) structures. At least one of the first type region and the second type region has one or more intra-well STI structures formed therein for isolating semiconductor devices formed within a same polarity well. The inter-well STI structures are formed at a substantially same depth with respect to the intra-well STI structures. A main well region is formed such that a bottom of the main well region is disposed above a bottom of the inter-well and intra-well STI features. One or more deep well regions couple the main well regions otherwise isolated by the intra-well STI structures, wherein the deep well regions are spaced away from the inter-well STI structures.
摘要翻译：半导体器件结构包括限定在衬底中的第一类型区域和第二类型区域，第一类型区域和第二类型区域被一个或多个阱间浅沟槽隔离（STI）结构隔开。第一类型区域和第二类型区域中的至少一个具有形成在其中的一个或多个井内STI结构，用于隔离在相同极性内形成的半导体器件。井间STI结构相对于井内STI结构形成在基本相同的深度。形成主阱区域，使得主阱区域的底部设置在井间和井内STI特征的底部之上。一个或多个深井区域连接主井区域，否则由井内STI结构隔离，其中深井区域与井间STI结构间隔开。

5. 发明授权

US08946866B2 Microelectronic substrate having removable edge extension element 有权
标题翻译：具有可移除边缘延伸元件的微电子基板
公开(公告)号：US08946866B2
公开(公告)日：2015-02-03
申请号：US13490239
申请日：2012-06-06
申请人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
发明人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
IPC分类号： H01L29/06 , G03F7/20
CPC分类号： G03F7/70691 , G03F7/70341 , G03F7/70808
摘要： An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.
摘要翻译：提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。这种物品包括具有前表面，与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。前表面是物品的主要表面。具有前表面，后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。以这种方式，形成连续表面，其包括边缘延伸元件的前表面，该边缘延伸元件从微电子基底的周边边缘和微电子基底的前表面横向延伸，连续表面基本上共平面且平坦，周缘连接到内边缘。

6. 发明申请

US20140061930A1 OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE 有权
标题翻译：通过掩蔽和反应离子蚀刻（RIE）技术的超耐性
公开(公告)号：US20140061930A1
公开(公告)日：2014-03-06
申请号：US13604660
申请日：2012-09-06
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
摘要翻译：提供了一种方法，其包括首先根据第一掩模蚀刻衬底。第一蚀刻在衬底中形成第一深度的第一蚀刻特征。第一蚀刻还在衬底中形成条条开口。然后可以用填充材料填充条子开口。可以通过去除第一掩模的一部分来形成第二掩模。可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

7. 发明授权

US08609534B2 Electrical fuse structure and method of fabricating same 有权
标题翻译：电熔丝结构及其制造方法
公开(公告)号：US08609534B2
公开(公告)日：2013-12-17
申请号：US12890941
申请日：2010-09-27
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L21/4763
CPC分类号： H01L23/5256 , H01L21/76805 , H01L21/76807 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
摘要翻译：使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。通孔开口位于顶部并连接到金属层。双镶嵌结构还包括线路开口和通孔开口内的导电特征。电介质间隔物也存在于线路开口和通孔开口内。介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。因此，提供了节省空间的高编程效率电熔丝。

8. 发明申请

US20130328208A1 DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME 有权
标题翻译：双重对等双向对联方案
公开(公告)号：US20130328208A1
公开(公告)日：2013-12-12
申请号：US13490542
申请日：2012-06-07
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76819 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
摘要翻译：在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。之后形成第二电介质材料层。在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的第一条金属线。形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

9. 发明申请

US20130112462A1 Metal Alloy Cap Integration 审中-公开
标题翻译：金属合金盖整合
公开(公告)号：US20130112462A1
公开(公告)日：2013-05-09
申请号：US13290557
申请日：2011-11-07
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H05K1/09 , H05K3/00
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76849 , H01L21/76877 , H01L21/76882 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T29/49124 , H01L2924/00
摘要： A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer.
摘要翻译：包括金属合金覆盖层的金属互连结构及其制造方法。互连特征内的原始沉积的合金覆盖层元件将扩散到并分离到金属互连的顶表面上。金属合金覆盖材料沉积在回流铜表面上，并且不物理地与互连特征的侧壁接触。因此，互连结构中的残余合金元素的电阻率冲击降低。也就是说，在金属互连结构的特征内部存在合金元素的减少。金属互连结构包括具有凹陷线的介电层，侧壁上的衬垫材料，铜材料，合金盖和覆盖层。

10. 发明申请

US20130069161A1 INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP 有权
标题翻译：具有选择性金属盖的集成电路结构
公开(公告)号：US20130069161A1
公开(公告)日：2013-03-21
申请号：US13233064
申请日：2011-09-15
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L29/42372 , H01L21/28247 , H01L21/76834 , H01L21/7685 , H01L21/76856 , H01L21/76888 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/78
摘要： Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.
摘要翻译：在栅极上利用选择性地形成和至少部分氧化的金属盖形成集成电路结构的方法以及相关联的结构。在一个实施例中，一种方法包括提供包括具有金属栅极的晶体管的前体结构; 在所述金属栅极的暴露部分上形成蚀刻停止层; 至少部分氧化所述蚀刻停止层; 以及在所述至少部分氧化的蚀刻停止层上形成电介质层。

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