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41. 发明授权

US06174762B1 Salicide device with borderless contact 失效
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06174762B1
公开(公告)日：2001-01-16
申请号：US09260311
申请日：1999-03-02
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L218234
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

42. 发明授权

US6111425A Very low power logic circuit family with enhanced noise immunity 有权
标题翻译：超低功耗逻辑电路系列，具有增强的抗噪声能力
公开(公告)号：US6111425A
公开(公告)日：2000-08-29
申请号：US173436
申请日：1998-10-15
申请人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K19/003 , H03K3/356 , H03K19/173 , H03K17/16
CPC分类号： H03K3/356113 , H03K19/1738
摘要： A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.
摘要翻译：一个非常低功率的逻辑电路系列，有利地提供1）保持高性能，2）显着降低的功耗，和3）增强的抗噪声能力。在第一组实施例中，使用双轨互补逻辑信号来提高对外部噪声的电路抗扰性并且减少由逻辑电路本身产生的噪声。本发明的接收机部分包括具有两个门到两个源的交叉耦合的两个输入FET。在一个优选实施例中，接收器和驱动器部分都连接在具有所有N个通道驱动器的中继器中。第二组实施例在不平衡接收机中具有单侧输入，包括到栅极N沟道的交叉耦合源极和栅极P沟道输出晶体管的交叉耦合漏极。

43. 发明授权

US6107125A SOI/bulk hybrid substrate and method of forming the same 有权
标题翻译： SOI /散装混合基板及其形成方法
公开(公告)号：US6107125A
公开(公告)日：2000-08-22
申请号：US187292
申请日：1998-11-05
申请人： Mark A. Jaso , Jack A. Mandelman , William R. Tonti , Matthew R. Wordeman
发明人： Mark A. Jaso , Jack A. Mandelman , William R. Tonti , Matthew R. Wordeman
IPC分类号： H01L21/20 , H01L21/76 , H01L21/762 , H01L21/84 , H01L27/12 , H01L21/00
CPC分类号： H01L21/84 , H01L21/7624 , H01L27/1203
摘要： A semiconductor device having areas that are semiconductor on insulator ("SOI") and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.
摘要翻译：提供了具有半导体绝缘体（“SOI”）和作为本体的单晶半导体区域的区域的半导体器件，其中可以形成导电间隔物以将SOI区域电连接到地，以克服浮体效应，可以与SOI发生。此外，可以在导电间隔物的表面上形成绝缘间隔物，以将SOI区域与大块区域电隔离。提供了制造这两种产品的新方法，其中由于牺牲抛光层的沉积，外延生长的单晶体区域不需要选择性地生长。

44. 发明授权

US5909400A Three device BICMOS gain cell 失效
标题翻译：三器件BICMOS增益单元
公开(公告)号：US5909400A
公开(公告)日：1999-06-01
申请号：US917630
申请日：1997-08-22
申请人： Claude Louis Bertin , John Atkinson Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude Louis Bertin , John Atkinson Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/405 , G11C11/406 , G11C11/34
CPC分类号： G11C11/406 , G11C11/405
摘要： A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer periods of time before a refresh operation is required, requires a smaller storage capacitance than a traditional DRAM cell, and can be produced commercially at lower costs than are presently available. In a preferred embodiment, the gain cell comprises an n channel metal oxide semiconductor field effect write transistor having its gate connected to a write word line WLw. Its drain is connected to a storage node Vs having a storage capacitance Cs associated therewith, and its source is connected to a write bit line BLw. An n channel metal oxide semiconductor field effect read transistor has its gate connected to the storage node Vs and its source connected to a read word line WLr. A PNP transistor has its base connected to the drain of the read transistor and its emitter connected to a read bit line BLr. A second embodiment is constructed with p channel FETs and an NPN transistor.
摘要翻译：具有两个FET和一个双极器件的DRAM存储器的非破坏性读取，三器件BICMOS增益单元。增益单元具有改进的访问时间（更低的延迟），可以在需要刷新操作之前更长时间地操作，需要比传统DRAM单元更小的存储电容，并且可以以比目前可用的更低的成本在商业上生产。在优选实施例中，增益单元包括其栅极连接到写入字线WLw的n沟道金属氧化物半导体场效应写入晶体管。其漏极连接到具有与其相关联的存储电容Cs的存储节点Vs，并且其源极连接到写入位线BLw。 n沟道金属氧化物半导体场效应读取晶体管的栅极连接到存储节点Vs，其源极连接到读取字线WLr。 PNP晶体管的基极连接到读晶体管的漏极，其发射极连接到读位线BLr。第二实施例由p沟道FET和NPN晶体管构成。

45. 发明授权

US5547894A CMOS processing with low and high-current FETs 失效
标题翻译：具有低和高电流FET的CMOS处理
公开(公告)号：US5547894A
公开(公告)日：1996-08-20
申请号：US576184
申请日：1995-12-21
申请人： Jack A. Mandelman , Duane Galbi , James A. Slinkman , William R. Tonti
发明人： Jack A. Mandelman , Duane Galbi , James A. Slinkman , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A method of processing CMOS circuits provides up to three types of transistors (standard NFETs, PFETs and high current NFETs) without additional masking steps by the simultaneous implantation of the standard PFET and the high current NFET low doped source and drain implants and a separate implantation of the standard NFET.
摘要翻译：处理CMOS电路的方法提供多达三种类型的晶体管（标准NFET，PFET和高电流NFET），通过同时植入标准PFET和高电流NFET低掺杂源极和漏极注入以及单独注入，不需要额外的掩蔽步骤的标准NFET。

46. 发明授权

US08580646B2 Method of fabricating field effect transistors with low k sidewall spacers 失效
标题翻译：制造具有低k侧壁间隔物的场效应晶体管的方法
公开(公告)号：US08580646B2
公开(公告)日：2013-11-12
申请号：US12948805
申请日：2010-11-18
申请人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti
发明人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/336 , H01L21/331 , H01L21/425 , H01L21/26 , H01L21/42
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/268 , H01L29/665
摘要： Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.
摘要翻译：场效应晶体管和形成场效应晶体管的方法。场效应晶体管包括：半导体衬底中的沟道区上的栅极电介质; 栅电极上的栅电极; 在沟道区域的相对侧上的衬底中的相应源极/漏极; 靠近源极/漏极的栅电极的相对侧上的侧壁间隔物; 并且其中所述侧壁间隔物包括介电常数低于二氧化硅的介电常数且能够吸收激光辐射的材料。

47. 发明授权

US08232649B2 Structure for interconnect structure containing various capping materials for electrical fuse and other related applications 有权
标题翻译：包含用于电熔丝和其他相关应用的各种封盖材料的互连结构的结构
公开(公告)号：US08232649B2
公开(公告)日：2012-07-31
申请号：US13052662
申请日：2011-03-21
申请人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/58 , H01L23/62 , H01L29/00 , H01L27/10 , H01L29/73 , H01L29/74
CPC分类号： H01L23/5256 , H01L21/76829 , H01L21/76838 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
摘要翻译：为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。第二互连结构具有与第一界面结构不同的第二界面结构。

48. 发明授权

US08216909B2 Field effect transistor with air gap dielectric 有权
标题翻译：具有气隙电介质的场效应晶体管
公开(公告)号：US08216909B2
公开(公告)日：2012-07-10
申请号：US12547529
申请日：2009-08-26
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

49. 发明申请

US20120091556A1 VERTICAL SILICIDE E-FUSE 有权
标题翻译：垂直硅胶电子保险丝
公开(公告)号：US20120091556A1
公开(公告)日：2012-04-19
申请号：US12904435
申请日：2010-10-14
申请人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
发明人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.
摘要翻译：一种制造电熔丝的装置和方法包括：衬底，衬底上的图案化栅极绝缘体，以及图案化栅极绝缘体上的图案化栅极导体。图案化的栅极导体具有侧壁和顶部。硅化物接触图案化栅极导体的侧壁，图案化栅极导体的顶部以及与图案化栅极绝缘体和图案化栅极导体相邻的衬底区域。

50. 发明申请

US20110169127A1 STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS 有权
标题翻译：用于电气保险丝和其他相关应用的各种接头材料互连结构的结构
公开(公告)号：US20110169127A1
公开(公告)日：2011-07-14
申请号：US13052662
申请日：2011-03-21
申请人： Louis L. HSU , William R. Tonti , Chih-Chao Yang
发明人： Louis L. HSU , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/525 , G06F17/50
CPC分类号： H01L23/5256 , H01L21/76829 , H01L21/76838 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
摘要翻译：为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。第二互连结构具有与第一界面结构不同的第二界面结构。

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