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1. 发明授权

US5909400A Three device BICMOS gain cell 失效
标题翻译：三器件BICMOS增益单元
公开(公告)号：US5909400A
公开(公告)日：1999-06-01
申请号：US917630
申请日：1997-08-22
申请人： Claude Louis Bertin , John Atkinson Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude Louis Bertin , John Atkinson Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/405 , G11C11/406 , G11C11/34
CPC分类号： G11C11/406 , G11C11/405
摘要： A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer periods of time before a refresh operation is required, requires a smaller storage capacitance than a traditional DRAM cell, and can be produced commercially at lower costs than are presently available. In a preferred embodiment, the gain cell comprises an n channel metal oxide semiconductor field effect write transistor having its gate connected to a write word line WLw. Its drain is connected to a storage node Vs having a storage capacitance Cs associated therewith, and its source is connected to a write bit line BLw. An n channel metal oxide semiconductor field effect read transistor has its gate connected to the storage node Vs and its source connected to a read word line WLr. A PNP transistor has its base connected to the drain of the read transistor and its emitter connected to a read bit line BLr. A second embodiment is constructed with p channel FETs and an NPN transistor.
摘要翻译：具有两个FET和一个双极器件的DRAM存储器的非破坏性读取，三器件BICMOS增益单元。增益单元具有改进的访问时间（更低的延迟），可以在需要刷新操作之前更长时间地操作，需要比传统DRAM单元更小的存储电容，并且可以以比目前可用的更低的成本在商业上生产。在优选实施例中，增益单元包括其栅极连接到写入字线WLw的n沟道金属氧化物半导体场效应写入晶体管。其漏极连接到具有与其相关联的存储电容Cs的存储节点Vs，并且其源极连接到写入位线BLw。 n沟道金属氧化物半导体场效应读取晶体管的栅极连接到存储节点Vs，其源极连接到读取字线WLr。 PNP晶体管的基极连接到读晶体管的漏极，其发射极连接到读位线BLr。第二实施例由p沟道FET和NPN晶体管构成。

2. 发明授权

US06531410B2 Intrinsic dual gate oxide MOSFET using a damascene gate process 有权
公开(公告)号：US06531410B2
公开(公告)日：2003-03-11
申请号：US09795610
申请日：2001-02-27
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L2131
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

3. 发明授权

US06339559B1 Decode scheme for programming antifuses arranged in banks 失效
标题翻译：用于在银行中排列的编程反熔丝的解码方案
公开(公告)号：US06339559B1
公开(公告)日：2002-01-15
申请号：US09781883
申请日：2001-02-12
申请人： Claude Louis Bertin , John Atkinson Fifield , Nicholas Martin van Heel
发明人： Claude Louis Bertin , John Atkinson Fifield , Nicholas Martin van Heel
IPC分类号： G11C1716
CPC分类号： G11C17/16
摘要： Described is an antifuse array comprising a plurality of antifuse elements and a plurality of cell plates. Each of the antifuse elements comprises a programming transistor and one of the cell plates. The programming transistor and the cell plate of each antifuse element are both activated to program the antifuse element. Each of the cell plates is coupled to a portion of the plurality of antifuse elements and to one of a plurality of decode circuits, and the decode circuits selectively activate its coupled cell plate. With a preferred embodiment, a multitude of interconnect lines are connected to the antifuses and in particular, each interconnect line intersects each of the cell plates and is associated with one antifuse in each group of antifuses. With this preferred embodiment, the array of antifuses are decoded by predecoding one of the cell plates by elevating the cell plate voltage from ground to a program voltage, and decoding one of the interconnect lines to program one of the antifuses. The intersection of the cell plate set to a program voltage and the decoded interconnect line results in programming a unique antifuse.
摘要翻译：描述了包括多个反熔丝元件和多个单元板的反熔丝阵列。每个反熔丝元件包括编程晶体管和单元板之一。每个反熔丝元件的编程晶体管和单元板都被激活以对反熔丝元件进行编程。每个单元板耦合到多个反熔丝元件的一部分和多个解码电路中的一个，并且解码电路选择性地激活其耦合的单元板。利用优选实施例，多个互连线连接到反熔丝，并且特别地，每个互连线与每个单元板相交，并且在每组反熔丝组中与一个反熔丝相关联。利用该优选实施例，通过将单元板电压从地面升高到编程电压，对单元板中的一个进行预解码，并解码其中一条互连线以对其中一个反熔丝进行编译，对反熔丝阵列进行解码。单元板设置为编程电压和解码的互连线的交点导致编程独特的反熔丝。

4. 发明授权

US07276775B2 Intrinsic dual gate oxide MOSFET using a damascene gate process 失效
标题翻译：使用镶嵌栅极工艺的本征双栅极氧化物MOSFET
公开(公告)号：US07276775B2
公开(公告)日：2007-10-02
申请号：US10329593
申请日：2002-12-26
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L29/04 , H01L31/036 , H01L27/10 , H01L29/00
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.
摘要翻译：当与包括（a）在结构上形成具有开口的掩模的方法一起使用时，镶嵌或非镶嵌加工，所述开口具有侧壁; （b）通过开口将抑制物质注入所述结构中，以在所述结构中形成抑制区域; 和（c）在所述开口中的结构上生长电介质层，其中抑制区域部分抑制电介质层的生长能够形成半导体结构，例如包括双重厚度介电层的MOSFET或反熔丝。或者，可以通过用有助于电介质层生长的结构中形成增强区的介电生长增强物种代替上述抑制物质来形成双重厚度电介质。

5. 发明授权

US06570806B2 System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor 有权
标题翻译：用于改善DRAM单电池故障定位和模块级柔性修复的系统和方法以及通用激光熔丝/反熔丝锁芯
公开(公告)号：US06570806B2
公开(公告)日：2003-05-27
申请号：US09891025
申请日：2001-06-25
申请人： Claude Louis Bertin , John Atkinson Fifield , Nicholas Martin Van Heel , Jason Timothy Varricchione
发明人： Claude Louis Bertin , John Atkinson Fifield , Nicholas Martin Van Heel , Jason Timothy Varricchione
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： A universal fuse latch device includes a latch circuit receiving an electrical signal for initializing the latch circuit to a first state; one or more legs connected at the latch node, with a first leg implementing a fuse type element capable of transitioning the latch from the first state to a second state; and a second leg including an anti-fuse type element, wherein the fuse latch is provided with a fuse resistance trip point to ensure adequate reading of one of the fuse and anti-fuse type elements. The universal fuse latch device may be part of a programmable fuse bank including a plurality of information fuse latches for storing redundancy information in a memory system and capable of being simultaneously interrogated. A master fuse control device comprising the universal fuse latch circuit is programmed in accordance with a priority of legs to be interrogated in the information fuse latches.
摘要翻译：通用熔丝锁存装置包括一个锁存电路，其接收用于将锁存电路初始化为第一状态的电信号; 一个或多个腿连接在锁存节点处，第一腿实现能够将锁存器从第一状态转换到第二状态的熔丝类型元件; 以及包括反熔丝型元件的第二支脚，其中所述熔丝闩锁设置有熔丝电阻跳变点，以确保所述保险丝和反熔丝型元件之一的充分读取。通用熔丝锁定装置可以是可编程熔丝库的一部分，其包括用于将冗余信息存储在存储器系统中并且能够被同时询问的多个信息熔丝锁存器。包括通用熔丝锁存电路的主熔丝控制装置根据要在信息熔丝锁存器中询问的支腿的优先级进行编程。

6. 发明授权

US06455778B2 Micro-flex technology in semiconductor packages 失效
公开(公告)号：US06455778B2
公开(公告)日：2002-09-24
申请号：US09894692
申请日：2001-06-28
申请人： Claude Louis Bertin , Thomas George Ference , Wayne John Howell , John Atkinson Fifield
发明人： Claude Louis Bertin , Thomas George Ference , Wayne John Howell , John Atkinson Fifield
IPC分类号： H01L3300
CPC分类号： H01L23/49816 , H01L23/49524 , H01L23/49531 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06579 , H01L2924/00013 , H01L2924/01079 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H05K1/0228 , H01L2924/00014 , H01L2224/29099 , H01L2924/00 , H01L2924/00012
摘要： Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

7. 发明授权

US06444490B1 Micro-flex technology in semiconductor packages 有权
公开(公告)号：US06444490B1
公开(公告)日：2002-09-03
申请号：US09894706
申请日：2001-06-28
申请人： Claude Louis Bertin , Thomas George Ference , Wayne John Howell , John Atkinson Fifield
发明人： Claude Louis Bertin , Thomas George Ference , Wayne John Howell , John Atkinson Fifield
IPC分类号： H01L2144
摘要： Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

8. 发明授权

US06300687B1 Micro-flex technology in semiconductor packages 失效
标题翻译：半柔性技术在半导体封装中
公开(公告)号：US06300687B1
公开(公告)日：2001-10-09
申请号：US09105382
申请日：1998-06-26
申请人： Claude Louis Bertin , Thomas George Ference , Wayne John Howell , John Atkinson Fifield
发明人： Claude Louis Bertin , Thomas George Ference , Wayne John Howell , John Atkinson Fifield
IPC分类号： H01L2348
CPC分类号： H01L23/49816 , H01L23/49524 , H01L23/49531 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06579 , H01L2924/00013 , H01L2924/01079 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H05K1/0228 , H01L2924/00014 , H01L2224/29099 , H01L2924/00 , H01L2924/00012
摘要： Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of a chip at increased frequencies.
摘要翻译：公开了薄膜微纤维双绞线对和其它连接器。半导体封装包括将至少一个芯片电连接到另一层封装的微技术技术。根据本发明的诸如薄膜双绞线对连接器的Microflex连接器提供优异的电气性能，其包括降低的线路电感，集成的无源部件的结合以及将离散的被动和有源部件附接到微反射镜。所有这些特性使得芯片能够以更高的频率工作。

9. 发明授权

US5880988A Reference potential for sensing data in electronic storage element 失效
标题翻译：电子存储元件中感应数据的参考电位
公开(公告)号：US5880988A
公开(公告)日：1999-03-09
申请号：US893797
申请日：1997-07-11
申请人： Claude Louis Bertin , John Atkinson Fifield , Russell James Houghton , Christopher Paul Miller , William Robert Patrick Tonti
发明人： Claude Louis Bertin , John Atkinson Fifield , Russell James Houghton , Christopher Paul Miller , William Robert Patrick Tonti
IPC分类号： G11C11/401 , G11C7/14 , G11C5/06
CPC分类号： G11C7/14
摘要： A column of an integrated memory circuit includes two bit lines each with a right half and a left half and a plurality of similar memory cells connected to each half of each bit line. One of the memory cells connected to each line is used as a reference and the other cells are used for data storage. Each half of each bit line is connected to a sense node of a sense amplifier latch through an independently controlled transistor switch. To read the data from the first half of the first bit line, the transistors connecting the first half of the first bit line to the sense node is turned on and the transistor connecting the second half of the first bit line to the sense node is turned off. Both transistor switches connecting respective halves of the other bit line to the other sense node are turned on. Each half of each bit line includes approximately the same effective load. The load applied to the first sense node is thus about half of the load applied to the second sense node. Access switches are opened to access the value stored in the data memory element and the reference data element and the resulting potential in the bit lines are significantly different whether the same value is stored or not, due to the different loads. Preferably, the output of the memory elements is selected so that the reference potential is about midway between the potential in a bit line half connected to a memory element storing a high value and a low value.
摘要翻译：集成存储器电路的列包括两个位线，每个位线具有连接到每个位线的每一半的右半部分和左半部分以及多个相似的存储器单元。连接到每条线的存储器单元之一用作参考，其他单元用于数据存储。每个位线的每一半通过独立控制的晶体管开关连接到读出放大器锁存器的感测节点。为了读取来自第一位线的前半部分的数据，将第一位线的前半部分连接到感测节点的晶体管导通，并且将第一位线的第二半部分连接到感测节点的晶体管被转换关闭将另一个位线的相应两半连接到另一个感测节点的两个晶体管开关导通。每个位线的每一半包括大致相同的有效负载。因此，施加到第一感测节点的负载大约是施加到第二感测节点的负载的一半。打开访问开关以访问存储在数据存储器元件中的值和参考数据元素，并且由于不同的负载，位线中产生的电位是否与存储相同的值是显着不同的。优选地，存储器元件的输出被选择为使得参考电位在连接到存储高值和低值的存储元件的位线半部中的电位之间的大约中间。

10. 发明申请

US20090256591A1 STRUCTURE FOR SYSTEMS AND METHODS OF MANAGING A SET OF PROGRAMMABLE FUSES ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于系统的结构和在集成电路上管理一组可编程熔丝的方法
公开(公告)号：US20090256591A1
公开(公告)日：2009-10-15
申请号：US12103519
申请日：2008-04-15
申请人： John Atkinson Fifield , Michael Richard Ouellette
发明人： John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H03K19/173
CPC分类号： H03K19/1733
摘要： Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.
摘要翻译：公开了一种用于在集成电路上管理一组可编程熔丝的系统和方法的设计结构。

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