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41. 发明专利

JPH01272147A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01272147A
公开(公告)日：1989-10-31
申请号：JP10031688
申请日：1988-04-25
申请人： HITACHI LTD
发明人： OTSUKA FUMIO , TSUCHIYA OSAMU
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L27/10 , H01L29/78
摘要： PURPOSE:To ensure the breakdown strength of an n-channel MISFET by making an insulating film on the sidewall of a p-channel MISFET smaller than that on the sidewall of the n-channel MISFET in a semiconductor integrated circuit device with a CMOS adopting LDD structure. CONSTITUTION:Length in the channel length direction of a semiconductor region 18 is constituted in size smaller than semiconductor regions 9 in a MISFETQn and a MISFETQS. That is, a sidewall insulating film 19 is organized so that length in the channel length direction is made smaller than a sidewall insulating film 16 in the MISFETQn and a sidewall insulating film 10 in the MISFETQS. The sidewall insulating film 19 is constructed in size smaller than 0.3mum such as 0.1mu-0.25mum on a 1.3mum process. That is, since the series resistance value of a semiconductor region (between a source region and a drain region) 20 can be lowered, current driving force can be increased while a section (between a source region and a drain region) between semiconductor regions 17 can be isolated, thus ensuring breakdown strength between the semiconductor regions 17.

42. 发明专利

JPH01145852A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01145852A
公开(公告)日：1989-06-07
申请号：JP30319287
申请日：1987-12-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKANO MITSUHIRO , UDO SHINJI , KOMATSU NOBUO , KASAMA YASUHIRO , TSUCHIYA OSAMU
IPC分类号： H01L27/10 , H01L21/76 , H01L21/8242 , H01L27/105 , H01L27/108
摘要： PURPOSE:To decrease soft errors, to form channel stopper regions at a boundary part and to improve breakdown strength in insulation and isolation at the boundary part, by increasing and optimizing the impurity concentration of a potential barrier layer in a memory cell array. CONSTITUTION:A channel stopper region 4A beneath a field insulating film 3, which specifies a region in a memory cell M in a DRAM, and a potential barrier layer 4B beneath the memory cell M are constituted in the same manufacturing step. At a boundary part between a memory cell array MA and a peripheral circuit region AL, the channel stopper region 4A or the potential barrier layer 4B and a channel stopper region 5 are overlapped by at least an amount equivalent to a deviated amount in mask alignment in the manufacturing process. Thus, the impurity concentration of the potential barrier layer 4A in the memory array MS can be increased and optimized. Therefore, soft errors can be decreased and the channel stopper regions 4A and 5 can be positively formed at the boundary part. In this way, the breakdown strength in insulation and isolation at the boundary part can be improved.

43. 发明专利

JP2001036034A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2001036034A
公开(公告)日：2001-02-09
申请号：JP20467399
申请日：1999-07-19
申请人： HITACHI LTD
发明人： OKAZAKI TSUTOMU , IKEDA YOSHIHIRO , TSUCHIYA OSAMU
IPC分类号： H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase process margins in photolithography and etching techniques for the formation of active regions by placing in a memory region a plurality of active regions having band-like planar shape at regular intervals in the direction of the width. SOLUTION: A semiconductor substrate 1 is oxidized by heating to form a pad insulating film 4 on the major surface of the semiconductor substrate 1. An insulating film 5 is formed thereon, and the pad insulating film 4 and the insulating film 5 are processed using photolithography and etching techniques so as to reduce line/space to minimum processing dimensions. Thus a plurality of the pad insulating films 4 and insulating films 5 extending in planar bandlike pattern are formed on the major surface of the semiconductor substrate 1 at regular intervals in the direction of their width. Therefore, the planar dimensions of patterns can be increased, and further process margins in photolithography and etching processes for patterning the insulating film 5 and the like can be enlarged.

44. 发明专利

JPH11345945A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11345945A
公开(公告)日：1999-12-14
申请号：JP15088898
申请日：1998-06-01
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KUBOTA KATSUHIKO , SUZUKI CHIKASHI , TADAKI YOSHITAKA , OGISHIMA JUNJI , TSUCHIYA OSAMU , ASAKURA HISAO , WATABE KOZO
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To realize a DRAM having the excellent refleshing characteristics without decreasing the threshold voltage of a memory-cell selecting MISFET (metal-insulator semiconductor field-effect transistor). SOLUTION: In a channel region, high-concentration boron for adjusting a threshold voltage is introduced. At the lower part of a pair of n-type semiconductor region constituting a source and a drain, an electric-field alleviating layer constituted of phosphor is formed. Furthermore, at the sloping region of the concentration distribution of the boron for adjusting the threshold voltage, arsenic is introduced. At the region, wherein the arsenic is introduced, the concentration distribution of the above described boron becomes low. The impurity concentration of the semiconductor substrate at the metallurgical bonding position of the electric-field alleviating layer and the semiconductor substrate becomes low to the degree of 1×10 cm .

45. 发明专利

JPH11111868A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11111868A
公开(公告)日：1999-04-23
申请号：JP26969397
申请日：1997-10-02
申请人： HITACHI LTD
发明人： IKEDA YOSHIHIRO , OKAZAKI TSUTOMU , TSUCHIYA OSAMU
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a gate electrode provided with the side wall spacer of high performance, high reliability and its manufacture. SOLUTION: In an AND type FLASH memory or the like, the side wall spacer is provided on the side wall of a gate electrode 6 on a silicon oxide film (gate insulation film) 5. The side wall spacer is provided with a silicon oxide film 9 formed by thermally oxidizing the semiconductor area of the edge of the gate electrode 6 and a well 4 on a semiconductor substrate (substrate) 1 at the lower part of the edge, etc., a silicon oxide film 10 formed on the side wall of the silicon oxide film 9 by using a CVD method, a silicon nitride film 14 formed on the side wall of the silicon oxide film 10, and a silicon oxide film 15 formed on the side wall of the silicon nitride film 14.

46. 发明专利

JPH1064285A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH1064285A
公开(公告)日：1998-03-06
申请号：JP21828196
申请日：1996-08-20
申请人： HITACHI LTD
发明人： KATO MASATAKA , TSUCHIYA OSAMU , YADORI SHOJI , TANAKA TOSHIHIRO , ADACHI TETSUO
IPC分类号： G11C17/00 , G11C7/00 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To make possible the application of a micro memory cell and reduce an area of a memory chip, by impressing a voltage to a source, a drain diffusion layer step by step when electrons are pulled from a floating gate electrode. SOLUTION: When electrons are pulled out from a floating gate electrode, a positive voltage is impressed to a diffusion layer opposite to a diffusion layer where the electrons are to be pulled, thereby to decrease a maximum voltage impressed between a source terminal and a drain terminal. Further, a positive voltage is impressed to a control gate electrode of a memory cell where the electrons are not pulled and a diffusion layer not in a pull-out direction is let to float. A write/erasure method for the memory cell which is not restricted by a voltage decrease inviting a problematic punch-through current between the source and drain when the memory cell is microminiaturized, in other words, not restricted by a decrease of a punch-through voltage is obtained, and a memory chip can be very small.

47. 发明专利

JPH08250681A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250681A
公开(公告)日：1996-09-27
申请号：JP6407496
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE: To flatten the surface of an interlayer insulating film by filling an interval between lower electrode layers with an interlayer insulating layer by making thicker the thickness of the interlayer insulating film than the specific amount of a distance between first electrodes of a memory cell where the first electrodes of the memory cell adjoin with a minimum interval. CONSTITUTION: This device comprises a plurality of word lines 27 that constitute a gate electrode 27 of a memory cell selecting MISFETQS, a first electrode 37 extending onto the word lines, and a second electrode 35 provided oppositely to the first electrode 37 through a dielectric 36. An interlayer insulating film 53 is provided between a second electrode 37 and a wiring 36. The first electrode 37 is independently of each memory cell M, and the second electrode 35 is formed commonly to a plurality of the memory cells. The interlayer insulating film 53 is constructed to be thicker than 1/2 of a distance between the first electrodes 37 where the first electrodes of the memory cell M adjoin with a minimum interval. Hereby, an interval between the lower layer electrode layers 35 is filled with the interlayer insulating film 53 to flatten the surface of the interlayer insulating film 53.

48. 发明专利

JPH08250601A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08250601A
公开(公告)日：1996-09-27
申请号：JP6404696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve hot carrier withstand voltage by making virtually equal the dimensions in the direction of gate length of the semiconductor regions of low impurity concentration, which form the LDD structure of a first and a second MISFETs, respectively. CONSTITUTION: The n-channel MISFETs Qn of an input/output stage circuit and an internal circuit are composed of a gate insulating film 26, a gate electrode 27, a n-type semiconductor region 29, and a n--type semiconductor region 32, respectively. The side wall spacers 31 of these n-channel MISFETs Qn are virtually the same in size in the direction of gate length. The gate length of the n-channel MISFET Qn in the input/output stage circuit is made larger than that of the n-channel MISFET Qn in the internal circuit. Further, the n-type semiconductor regions 29 forming the LDD structure of the n-channel MISFETs are virtually the same in size in the direction of gate length. This improves hot carrier withstand voltage, and reduces threshold voltage drop with a lapse of time, which enables the improvement of electrical characteristics.

49. 发明专利

JPH08241969A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241969A
公开(公告)日：1996-09-17
申请号：JP6407696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the moisture-proof of a passivation film formed on an interconnection layer by a method wherein the film thickness of an insulating film formed on an aluminum interconnection is specified by using a CVD method in which tetraethoxysilane is used as a source gas. CONSTITUTION: A passivation film 56 is formed on interconnections 55 which are composed mainly of aluminum alloy films 55B. The passivation film 56 is constituted of a composite film in which each of a silicon oxide film 56A deposited by a C-CVD method by using tetraethoxysilane as a source gas and a silicon nitride film 56B deposited by a plasma CVD method have been laminated in order. The silicon oxide film 56A at the lower layer of the passivation film 56 is constituted at a film thickness at 1/2 or higher of the interval between the interconnections 55 in regions in which the aspect ratio of the interval between the interconnections 55 to the film thickness of the interconnections 55 is at 1 or higher. By this constitution, the silicon oxide film 56A can be deposited at high step coverage at a low temperature at which the aluminum alloy films 55B for the interconnections 55 are not melted.

50. 发明专利

JPH056997A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH056997A
公开(公告)日：1993-01-14
申请号：JP18334591
申请日：1991-06-27
申请人： HITACHI LTD
发明人： OTSUKA FUMIO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , TSUCHIYA OSAMU , SUGIURA JUN
IPC分类号： H01L27/12 , H01L29/78 , H01L29/786
摘要： PURPOSE:To facilitate high integration even in the case of incorporating a level sensor or a timer by arranging the constitution such that a drain current flows to the transistor made in a semiconductor substrate when the gate potential on the semiconductor region made on the semiconductor substrate tops a certain value. CONSTITUTION:First source and drain regions 4 are provided on one main surface of a semiconductor substrate 1, and a first insulating film 2 is made on one main surface between these regions 4. A semiconductor region 3 is provided on the first insulating film 2, and second source and drain regions 7 are provided on the top of this region 3. A second insulating film 5 is provided on the main surface of the semiconductor region 3 between these regions 7, and a gate electrode 6 is provided on this insulating film 5. And by the gate potential added to a gate electrode 6, the substrate current flowing in the semiconductor region 3, in its turn, the potential of the substrate 1 in the semiconductor region 3 is changed, whereby the current flowing between the first source and drain is controlled. Hereby, a semiconductor device can be made in small occupancy area, and the degree of integration can be improved.

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