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41. 发明申请

US20070045748A1 Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权
标题翻译：将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法
公开(公告)号：US20070045748A1
公开(公告)日：2007-03-01
申请号：US11211956
申请日：2005-08-25
申请人： Roger Booth , Jack Mandelman , William Tonti
发明人： Roger Booth , Jack Mandelman , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译：通过大马士革方法在公共基板上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

42. 发明申请

US20060286781A1 Crystal imprinting methods for fabricating subsrates with thin active silicon layers 失效
标题翻译：用于制造具有薄的有源硅层的次级层的晶体压印方法
公开(公告)号：US20060286781A1
公开(公告)日：2006-12-21
申请号：US11154907
申请日：2005-06-16
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L29/045 , H01L21/84 , H01L27/1203
摘要： Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.
摘要翻译：通过晶体压印或镶嵌法在绝缘基板上形成由活性硅层薄的特征的半导体结构的方法。所述方法包括图案化绝缘层以限定多个孔，用非晶硅填充图案化绝缘层中的孔以限定多个非晶硅特征，以及重新生长非晶硅特征以限定薄的有源硅层，的再生硅特征。可以重新生长非晶硅特征，使得数量具有第一晶体取向，而另一数目具有不同的第二晶体取向。

43. 发明申请

US20050087814A1 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US20050087814A1
公开(公告)日：2005-04-28
申请号：US10995444
申请日：2004-11-23
申请人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
发明人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94 , H01L21/8238
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

44. 发明申请

US20070190740A1 ENHANCED SILICON-ON-INSULATOR (SOI) TRANSISTORS AND METHODS OF MAKING ENHANCED SOI TRANSISTORS 审中-公开
标题翻译：增强型硅绝缘体（SOI）晶体管及其制造增强型SOI晶体管的方法
公开(公告)号：US20070190740A1
公开(公告)日：2007-08-16
申请号：US11733249
申请日：2007-04-10
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/76
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

45. 发明申请

US20070013001A1 Epitaxial imprinting 失效
标题翻译：外延印记
公开(公告)号：US20070013001A1
公开(公告)日：2007-01-18
申请号：US11182381
申请日：2005-07-15
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L27/12 , H01L27/01
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/84 , H01L27/1203
摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.
摘要翻译：本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。

46. 发明申请

US20060234428A1 METHODS OF IMPLEMENTING AND ENHANCED SILICON-ON-INSULATOR (SOI) BOX STRUCTURES 失效
标题翻译：实施和增强硅绝缘体（SOI）盒结构的方法
公开(公告)号：US20060234428A1
公开(公告)日：2006-10-19
申请号：US11106004
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/66772 , H01L21/84 , H01L23/5252 , H01L27/1203 , H01L2924/0002 , Y10S438/928 , H01L2924/00
摘要： Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.
摘要翻译：提供了增强的绝缘体上硅（SOI）掩埋氧化物（BOX）结构和方法来实现增强的SOI BOX结构。将氧注入步骤从背面进行到薄化的硅衬底层。退火步骤从硅衬底层中的氧注入形成厚的掩埋氧化物（BOX）区域。氧注入步骤在氧植入物附近形成隔离区域。背侧注入步骤选择性地掺杂用于形成包括所选择的抗熔丝（AF）器件的SOI器件的SOI器件的隔离区域以及包括PFET和NFET器件的SOI晶体管的隔离区域。

47. 发明申请

US20060231892A1 Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors 失效
标题翻译：增强的绝缘体上硅（SOI）晶体管和制造增强型SOI晶体管的方法
公开(公告)号：US20060231892A1
公开(公告)日：2006-10-19
申请号：US11106002
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L27/12
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

48. 发明申请

US20060172499A1 STRUCTURE AND METHOD FOR THIN BOX SOI DEVICE 有权
标题翻译：薄盒SOI器件的结构与方法
公开(公告)号：US20060172499A1
公开(公告)日：2006-08-03
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, comprising providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

49. 发明申请

US20070145373A1 EPITAXIAL IMPRINTING 失效
标题翻译：外观印刷
公开(公告)号：US20070145373A1
公开(公告)日：2007-06-28
申请号：US11684306
申请日：2007-03-09
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L31/00 , C30B21/04 , H01L29/04 , H01L29/00
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/84 , H01L27/1203
摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.
摘要翻译：本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。

50. 发明申请

US20070284669A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 审中-公开
公开(公告)号：US20070284669A1
公开(公告)日：2007-12-13
申请号：US11838934
申请日：2007-08-15
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/76
CPC分类号： B07C5/344 , G01R31/2831
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

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