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1. 发明申请

US20050087814A1 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US20050087814A1
公开(公告)日：2005-04-28
申请号：US10995444
申请日：2004-11-23
申请人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
发明人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94 , H01L21/8238
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

2. 发明申请

US20070007601A1 Vertical MOSFET SRAM cell 审中-公开
标题翻译：垂直MOSFET SRAM单元
公开(公告)号：US20070007601A1
公开(公告)日：2007-01-11
申请号：US11509866
申请日：2006-08-25
申请人： Louis Hsu , Oleg Gluschenkov , Jack Mandelman , Carl Radens
发明人： Louis Hsu , Oleg Gluschenkov , Jack Mandelman , Carl Radens
IPC分类号： H01L21/8244 , H01L29/94 , H01L29/76
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
摘要翻译：形成SRAM单元装置的方法包括以下步骤。形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为形成在平面绝缘体上的平行岛的硅层。通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到到共同的身体层。形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。然后，连接FET晶体管以形成SRAM单元。

3. 发明申请

US20070210890A1 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US20070210890A1
公开(公告)日：2007-09-13
申请号：US11372387
申请日：2006-03-09
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01H85/04
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

4. 发明申请

US20060284250A1 Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates 失效
公开(公告)号：US20060284250A1
公开(公告)日：2006-12-21
申请号：US11154906
申请日：2005-06-16
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/045
摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

5. 发明申请

US20080079172A1 METHOD FOR FABRICATING AND BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS FORMATION OF HIGH-K AND LOW-K DIELECTRIC REGIONS 有权
标题翻译：同时形成高K和低K介电区域的制造和波形互连结构的方法
公开(公告)号：US20080079172A1
公开(公告)日：2008-04-03
申请号：US11939671
申请日：2007-11-14
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
摘要翻译：一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。在第一ILD中形成多个柱状气隙。使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

6. 发明申请

US20080067608A1 Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开
标题翻译：具有伪装配置的存储元件及其使用方法
公开(公告)号：US20080067608A1
公开(公告)日：2008-03-20
申请号：US11928663
申请日：2007-10-30
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L27/06
CPC分类号： H01L23/585 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。在另一方面，提供了体现在用于设计制造的机器可读介质或测试设计中的设计结构。提供了许多其他方面。

7. 发明申请

US20070120218A1 CMOS compatible shallow-trench efuse structure and method 失效
标题翻译： CMOS兼容浅沟槽结构和方法
公开(公告)号：US20070120218A1
公开(公告)日：2007-05-31
申请号：US11290890
申请日：2005-11-30
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L21/268 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.
摘要翻译：提供了包括位于半导体衬底（主体或绝缘体中半导体）的沟槽内的至少一个电子熔丝的半导体结构。根据本发明，电熔丝与位于半导体衬底内的掺杂区电接触。本发明还提供一种制造这种半导体结构的方法，其中嵌入式电熔丝基本上与沟槽隔离区域同时形成。

8. 发明申请

US20080059924A1 Design Structures Incorporating Interconnect Structures with Liner Repair Layers 有权
标题翻译：将连接结构与衬管修复层结合在一起的设计结构
公开(公告)号：US20080059924A1
公开(公告)日：2008-03-06
申请号：US11875345
申请日：2007-10-19
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： G06F17/50
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes an interconnect structure with a liner formed on roughened dielectric material in an insulating layer and a conformal liner repair layer bridging that breaches in the liner. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译：用于设计，制造或测试设计的机器可读介质中体现的设计结构。该设计结构包括互连结构，其具有在绝缘层中的粗糙化介电材料上形成的衬垫和桥接该衬里中的破损的保形衬里修复层。保形衬里修复层由诸如含钴材料的导电材料形成。保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。

9. 发明申请

US20070099326A1 eFuse and methods of manufacturing the same 有权
标题翻译： eFuse及其制造方法
公开(公告)号：US20070099326A1
公开(公告)日：2007-05-03
申请号：US11266740
申请日：2005-11-03
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是eFuse，包括（1）衬底的绝缘氧化物层上方的半导体层; （2）形成在半导体层中的二极管; 和（3）二极管上形成的硅化物层。提供了许多其他方面。

10. 发明申请

US20070210411A1 Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof 失效
标题翻译：具有位于不同高度的端子部分的电可编程熔丝结构及其制造方法
公开(公告)号：US20070210411A1
公开(公告)日：2007-09-13
申请号：US11372334
申请日：2006-03-09
申请人： William Hovis , Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： William Hovis , Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L21/82 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到保险丝元件的正交取向部分。

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