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1. 发明申请

US20080050903A1 ELECTRICALLY PROGRAMMABLE FUSE STRUCTURES WITH NARROWED WIDTH REGIONS CONFIGURED TO ENHANCE CURRENT CROWDING AND METHODS OF FABRICATING THEREOF 失效
标题翻译：电气可编程的保险丝结构，具有配置为提高电流消耗的窄幅区域及其制作方法
公开(公告)号：US20080050903A1
公开(公告)日：2008-02-28
申请号：US11876942
申请日：2007-10-23
申请人： Roger BOOTH , Jack Mandelman , William Tonti
发明人： Roger BOOTH , Jack Mandelman , William Tonti
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.
摘要翻译：提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

2. 发明申请

US20060125086A1 Modular heat sink decoupling capacitor array forming heat sink fins and power distribution interposer module 失效
标题翻译：模块化散热器去耦电容阵列形成散热鳍片和功率分配插件模块
公开(公告)号：US20060125086A1
公开(公告)日：2006-06-15
申请号：US11008798
申请日：2004-12-09
申请人： Roger Booth , Matthew Doyle , Don Gilliland , Brian Gregg , Lynn Landin , Thomas Liang , Ankur Patel , Dennis Wurth
发明人： Roger Booth , Matthew Doyle , Don Gilliland , Brian Gregg , Lynn Landin , Thomas Liang , Ankur Patel , Dennis Wurth
IPC分类号： H01L23/34
CPC分类号： H05K1/0231 , H01L23/3672 , H01L23/50 , H01L2924/0002 , H05K1/0203 , H05K3/301 , H05K2201/10454 , H05K2201/2018 , H01L2924/00
摘要： A modular heat sink decoupling capacitor array includes a plurality of modules, each defining parallel distributed decoupling plates, and each module forming a heat sink fin. Each module includes multiple spaced apart contacts for providing low inductance connections with an associated device. A power distribution interposer module is attached to a heat sink surface of the modular decoupling capacitor. The interposer module is used for implementing power delivery without using valuable ball grid array (BGA) connections and printed circuit board (PCB) layers.
摘要翻译：模块化散热器去耦电容器阵列包括多个模块，每个模块限定平行分布式去耦板，并且每个模块形成散热片。每个模块包括多个间隔开的触点，用于与相关联的装置提供低电感连接。功率分配插入器模块连接到模块化去耦电容器的散热器表面。内插器模块用于实现功率输送，而不使用有价值的球栅阵列（BGA）连接和印刷电路板（PCB）层。

3. 发明申请

US20050095429A1 Drapable diamond thin films and method for the preparation thereof 有权
标题翻译：可钻石金刚石薄膜及其制备方法
公开(公告)号：US20050095429A1
公开(公告)日：2005-05-05
申请号：US10698921
申请日：2003-10-31
申请人： Donnie Reinhard , Jes Asmussen , Michael Becker , Timothy Grotjohn , Thomas Schuelke , Roger Booth
发明人： Donnie Reinhard , Jes Asmussen , Michael Becker , Timothy Grotjohn , Thomas Schuelke , Roger Booth
IPC分类号： B32B9/00 , C23C16/01 , C23C16/27 , G02B1/10
CPC分类号： G02B1/10 , C23C16/01 , C23C16/274 , C23C16/277 , Y10T156/10 , Y10T428/30
摘要： Wetted thin diamond films which are drapable are described. The films are mounted on various substrates and used as windows for electromagnetic radiation or form a surface coating on an article of manufacture.
摘要翻译：描述了可浸透的薄金刚石薄膜。膜被安装在各种基底上并用作电磁辐射的窗口或在制品上形成表面涂层。

4. 发明申请

US20080050866A1 SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
标题翻译：在公共基板上集成大面积金属体和平面器件的半导体结构及其形成这样的半导体结构的方法
公开(公告)号：US20080050866A1
公开(公告)日：2008-02-28
申请号：US11927780
申请日：2007-10-30
申请人： Roger Booth , Jack Mandelman , William Tonti
发明人： Roger Booth , Jack Mandelman , William Tonti
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译：通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

5. 发明申请

US20080029843A1 E-Fuse and Method for Fabricating E-Fuses Integrating Polysilicon Resistor Masks 审中-公开
标题翻译：电子保险丝和电子熔丝的制造方法，集成多晶硅电阻掩模
公开(公告)号：US20080029843A1
公开(公告)日：2008-02-07
申请号：US11873197
申请日：2007-10-16
申请人： Roger Booth , William Hovis , Jack Mandelman , William Tonti
发明人： Roger Booth , William Hovis , Jack Mandelman , William Tonti
IPC分类号： H01L29/41
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.
摘要翻译：一种电熔丝和一种用于制造集成多晶硅电阻掩模的电子熔丝的方法，以及设置有被检体E熔丝回路的设计结构。电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

6. 发明申请

US20070265793A1 METHOD AND APPARATUS FOR IMPLEMENTING AUTOMATIC-CALIBRATION OF TDR PROBING SYSTEM 有权
标题翻译：实现TDR探测系统自动校准的方法与装置
公开(公告)号：US20070265793A1
公开(公告)日：2007-11-15
申请号：US11781372
申请日：2007-07-23
申请人： Roger Booth , Matthew Doyle , Lynn Landin , Thomas Liang , Ankur Patel
发明人： Roger Booth , Matthew Doyle , Lynn Landin , Thomas Liang , Ankur Patel
IPC分类号： G01R35/00
CPC分类号： G01R35/00
摘要： A method and apparatus are provided for implementing automatic-calibration of a Time Domain Reflectometer (TDR) probing apparatus. A calibration procedure is performed automatically each time a TDR probe is moved from a device under test (DUT). A current calibration TDR waveform is obtained and compared with a reference calibration TDR waveform, checking for deviations between the current and reference measurements. If a deviation is detected, then the user is notified and calibration is failed.
摘要翻译：提供了一种用于实现时域反射计（TDR）探测装置的自动校准的方法和装置。每次TDR探针从被测设备（DUT）移动时，都会自动执行校准程序。获得当前的校准TDR波形并与参考校准TDR波形进行比较，检查电流和参考测量之间的偏差。如果检测到偏差，则通知用户并校准失败。

7. 发明申请

US20070087556A1 Method and mesh reference structures for implementing Z-axis cross-talk reduction through copper sputtering onto mesh reference planes 有权
标题翻译：用于通过铜溅射实现Z轴串扰降低的网格参考平面的方法和网格参考结构
公开(公告)号：US20070087556A1
公开(公告)日：2007-04-19
申请号：US11250043
申请日：2005-10-13
申请人： Roger Booth , Matthew Doyle
发明人： Roger Booth , Matthew Doyle
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H05K1/0224 , H05K1/0253 , H05K3/16 , H05K2201/09681 , H05K2201/09736
摘要： A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh electrical holes in the mesh reference plane to reduce cross-talk, substantially without affecting mechanical flexibility.
摘要翻译：提供了一种实现Z轴串扰降低的方法和网格参考应用。包括网格轨迹的网格的网格参考平面形成为具有选定的厚度和宽度尺寸的网格轨迹对于参考电流分布有效。沉积导电涂层以填充网格参考平面中的网格电孔，以减少串扰，基本上不影响机械灵活性。

8. 发明申请

US20060286779A1 Patterned Silicon-on-Insulator layers and methods for forming the same 失效
标题翻译：图案化的绝缘体上层及其形成方法
公开(公告)号：US20060286779A1
公开(公告)日：2006-12-21
申请号：US11155029
申请日：2005-06-16
申请人： Roger Booth , Louis Hsu , Jack Mandelman , William Tonti
发明人： Roger Booth , Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/76 , H01L21/00
CPC分类号： H01L21/76243
摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
摘要翻译：在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。提供了许多其他方面。

9. 发明授权

US6144276A Planar transformer having integrated cooling features 失效
标题翻译：具有集成冷却功能的平面变压器
公开(公告)号：US6144276A
公开(公告)日：2000-11-07
申请号：US053790
申请日：1998-04-02
申请人： James Roger Booth
发明人： James Roger Booth
IPC分类号： H01F27/28 , H01F5/00 , H01F27/08
CPC分类号： H01F27/2876
摘要： A planar electromagnetic device, such as a planar transformer or planar inductor, is provided with features for cooling that are formed integrally with the windings of the planar device. In a preferred embodiment the planar device uses winding layers (200) having fin portions (116). In a first alternative embodiment a helical winding (500) is formed from a winding stamping (400) having fin portions (412). In a second alternative embodiment, tube portions (802) are formed in a winding stamping (700) used to form a helical winding.
摘要翻译：平面电磁装置，例如平面变压器或平面电感器，具有与平面装置的绕组一体形成的用于冷却的特征。在优选实施例中，平面装置使用具有翅片部分（116）的缠绕层（200）。在第一替代实施例中，螺旋绕组（500）由具有翅片部分（412）的卷绕冲压（400）形成。在第二替代实施例中，管部分（802）形成在用于形成螺旋绕组的卷绕冲压（700）中。

10. 发明申请

US20070262413A1 E-FUSE AND METHOD FOR FABRICATING E-FUSES INTEGRATING POLYSILICON RESISTOR MASKS 审中-公开
标题翻译：电子熔丝和电子熔模聚合多晶硅电阻掩模的方法
公开(公告)号：US20070262413A1
公开(公告)日：2007-11-15
申请号：US11382808
申请日：2006-05-11
申请人： Roger Booth , William Hovis , Jack Mandelman , William Tonti
发明人： Roger Booth , William Hovis , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An E-fuse and a method for fabricating an E-fuse are provided integrating polysilicon resistor masks. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.
摘要翻译：集成了多晶硅电阻掩模的电子熔丝和用于制造电熔丝的方法被提供。电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

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