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1. 发明申请

US20070170521A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 有权
公开(公告)号：US20070170521A1
公开(公告)日：2007-07-26
申请号：US11306827
申请日：2006-01-12
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

2. 发明申请

US20070284669A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 审中-公开
公开(公告)号：US20070284669A1
公开(公告)日：2007-12-13
申请号：US11838934
申请日：2007-08-15
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/76
CPC分类号： B07C5/344 , G01R31/2831
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

3. 发明申请

US20070127172A1 ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING 失效
标题翻译：使用光电传感器的需求电路功能执行
公开(公告)号：US20070127172A1
公开(公告)日：2007-06-07
申请号：US11275058
申请日：2005-12-06
申请人： Wagdi Abadeer , James Adkisson , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Michael Hauser , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , James Adkisson , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Michael Hauser , Jed Rankin , William Tonti
IPC分类号： H02H9/00
CPC分类号： H01L23/5256 , H01L23/525 , H01L27/14609 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.
摘要翻译：公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。一旦封装的芯片放置在系统中，也可以将ESD保护装置从输入焊盘断开。不需要额外的引脚。

4. 发明申请

US20070292996A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 有权
标题翻译：加工薄膜和薄膜的方法和结构以及可变的熔化到熔融间隙
公开(公告)号：US20070292996A1
公开(公告)日：2007-12-20
申请号：US11846544
申请日：2007-08-29
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthler , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthler , Jed Rankin , William Tonti
IPC分类号： H01L21/84
CPC分类号： B07C5/344 , G01R31/2831
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.
摘要翻译：公开了一种集成电路，其具有在相同基板上具有不同宽度和可变间隔的多个半导体散热片。形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET，或者替代地，各种单鳍和/或多鳍FET。

5. 发明申请

US20050186744A1 MOSFET with decoupled halo before extension 失效
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US20050186744A1
公开(公告)日：2005-08-25
申请号：US10785895
申请日：2004-02-24
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier, , Carl Radens , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier, , Carl Radens , William Tonti
IPC分类号： H01L21/28 , H01L21/336 , H01L21/425 , H01L21/8234 , H01L29/423
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/6659
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

6. 发明申请

US20050090049A1 High voltage N-LDMOS transistors having shallow trench isolation region 失效
公开(公告)号：US20050090049A1
公开(公告)日：2005-04-28
申请号：US10991936
申请日：2004-11-18
申请人： Wagdi Abadeer , Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L21/266 , H01L29/0653 , H01L29/086 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

7. 发明申请

US20070284659A1 METHOD OF FORMING HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION WITH DRAIN EXTENSIONS 审中-公开
标题翻译：形成具有泄漏扩展的浅层分离区域的高电压N-LDMOS晶体管的方法
公开(公告)号：US20070284659A1
公开(公告)日：2007-12-13
申请号：US11844573
申请日：2007-08-24
申请人： Wagdi Abadeer , Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L21/266 , H01L29/0653 , H01L29/086 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.
摘要翻译：公开了一种用于晶体管的方法和结构，该晶体管具有栅极，栅极下方的沟道区，沟道区一侧的源极区，与源极区沟道区相反侧的漏极区，浅沟槽在漏极区和沟道区之间的衬底中的隔离（STI）区，以及在STI区之下的漏极延伸。漏极延伸沿着STI区域的底部并沿着STI的边的一部分定位。沿着STI底部的漏极延伸部分可以包括不同于沿着STI侧面的漏极延伸部分的掺杂剂注入。沿着STI侧面的排水延伸部分从STI的底部延伸到部分沿着STI侧面的位置。 STI区域位于栅极的一部分之下。漏极延伸部在漏极区域和围绕STI的下周边的沟道区域之间提供导电路径。漏极区域比源极区域更靠近栅极定位。

8. 发明申请

US20060220174A1 E-Fuse and anti-E-Fuse device structures and methods 审中-公开
标题翻译：电子熔断器和反电子保险丝器件的结构和方法
公开(公告)号：US20060220174A1
公开(公告)日：2006-10-05
申请号：US11440199
申请日：2006-05-24
申请人： Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
发明人： Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods. Each of the three methods can be used with three different embodiments, a first embodiment is a polysilicon E-Fuse with a sub-minimum width polysilicon fuse line, a second embodiment is a work function altered/programmed self-aligned MOSFET E-Fuse with a sub-minimum width fuse line, and a third embodiment is a polysilicon MOSFET E-Fuse with a sub-minimum width fuse line which is programmed with a low trigger voltage snapback.
摘要翻译：使用标准光刻法来图案化和制造最终的多晶硅晶片成像结构，该结构小于正常允许光刻最小尺寸。提供了三种不同的方法来产生这样的次最小维度结构，第一种方法使用具有掩模的最小尺寸图案特征之间的亚最小空间的光刻掩模，第二种方法使用光刻掩模与次最小宽度方向点动或掩模的最小尺寸图案特征之间的偏移，第三种方法是第一和第二方法的组合。三种方法中的每一种可以与三种不同的实施例一起使用，第一实施例是具有亚最小宽度多晶硅熔丝线的多晶硅E熔丝，第二实施例是工作功能改变/编程的自对准MOSFET E-Fuse，具有亚最小宽度熔丝线，第三实施例是具有低电平触发电压快速编程的亚最小宽度熔丝线的多晶硅MOSFET E-Fuse。

9. 发明申请

US20060060938A1 Resettable fuse device and method of fabricating the same 有权
标题翻译：可复位保险丝装置及其制造方法
公开(公告)号：US20060060938A1
公开(公告)日：2006-03-23
申请号：US10948773
申请日：2004-09-23
申请人： Wagdi Abadeer , John Fifield , Robert Gauthier , William Tonti
发明人： Wagdi Abadeer , John Fifield , Robert Gauthier , William Tonti
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.
摘要翻译：在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20）源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52）以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和栅极区域的第二端通过结损耗完成。栅极电介质（30）和栅电极（40）形成在栅极区域上方。当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。

10. 发明申请

US20060249799A1 Concurrent fin-fet and thick body device fabrication 有权
公开(公告)号：US20060249799A1
公开(公告)日：2006-11-09
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

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