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41. 发明授权

US06903013B2 Method to fill a trench and tunnel by using ALD seed layer and electroless plating 有权
标题翻译：通过使用ALD种子层和化学镀填充沟槽和隧道的方法
公开(公告)号：US06903013B2
公开(公告)日：2005-06-07
申请号：US10439923
申请日：2003-05-16
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yong Ju , Jia Zhen Zheng
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yong Ju , Jia Zhen Zheng
IPC分类号： H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/28562 , H01L21/76843 , H01L21/76873 , H01L23/5227 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.
摘要翻译：已经开发了一种改进的方法，通过原子层沉积，ALD，用于化学镀铜的铜屏障和种子层，在镶嵌工艺中的填充沟槽和沟道或隧道开口，用于制造互连和电感器。概述本发明方法的工艺流程如下：（1）形成沟槽和通道，（2）铜屏障和晶种的原子层沉积，（3）铜的无电沉积，（4）化学机械抛光的过量铜，和（5）阻挡层沉积，SiN，形成铜互连和电感器。

42. 发明授权

US6100196A Method of making a copper interconnect with top barrier layer 有权
标题翻译：制造与顶部阻挡层的铜互连的方法
公开(公告)号：US6100196A
公开(公告)日：2000-08-08
申请号：US396254
申请日：1999-09-15
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002
摘要： A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

43. 发明授权

US5728621A Method for shallow trench isolation 失效
标题翻译：浅沟槽隔离方法
公开(公告)号：US5728621A
公开(公告)日：1998-03-17
申请号：US845870
申请日：1997-04-28
申请人： Jia Zhen Zheng , Charlie Wee Song Tay , Wei Lu , Lap Chan
发明人： Jia Zhen Zheng , Charlie Wee Song Tay , Wei Lu , Lap Chan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate wherein there is at least one first wide nitride region between two of the isolation trenches and at least one second narrow nitride region between another two of the isolation trenches. A high density plasma (HDP) oxide layer is deposited over the nitride layer filling the isolation trenches wherein the HDP oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer and wherein the difference in step heights of the HDP oxide between the first region and a region overlying an isolation trench is a first height. A layer of spin-on-glass is coated over the HDP oxide layer wherein the difference in step heights of the spin-on-glass material between the first region and the region overlying an isolation trench is a second height smaller than the first height. The spin-on-glass layer and portions of the HDP oxide layer in the first region are etched away. The spin-on-glass layer and HDP oxide layer remaining are polished away wherein the substrate is planarized.
摘要翻译：描述了形成平面化高质量氧化物浅沟槽隔离的新方法。覆盖衬垫氧化物层的氮化物层设置在半导体衬底的表面上。通过氮化物和衬垫氧化物层蚀刻多个隔离沟槽到半导体衬底中，其中在两个隔离沟槽之间存在至少一个第一宽氮化物区域和在另外两个隔离沟槽之间的至少一个第二窄氮化物区域。在填充隔离沟槽的氮化物层上沉积高密度等离子体（HDP）氧化物层，其中HDP氧化物在宽氮化物层上的第一区域中更厚地沉积，并且在第二区域上更薄地沉积在窄氮化物层上，并且其中在第一区域和覆盖隔离沟槽的区域之间的HDP氧化物的阶跃高度的差异是第一高度。在HDP氧化物层上涂覆一层旋涂玻璃，其中在第一区域和覆盖隔离沟槽的区域之间的旋涂玻璃材料的阶梯高度的差异是比第一高度小的第二高度。旋转玻璃层和第一区域中的HDP氧化物层的部分被蚀刻掉。抛光剩余的旋涂玻璃层和HDP氧化物层，其中衬底被平坦化。

44. 发明授权

US07250669B2 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US07250669B2
公开(公告)日：2007-07-31
申请号：US10909523
申请日：2004-08-02
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
IPC分类号： H01L29/00
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

45. 发明授权

US07238971B2 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US07238971B2
公开(公告)日：2007-07-03
申请号：US11123748
申请日：2005-05-04
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L29/732
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

46. 发明授权

US06869884B2 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 失效
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US06869884B2
公开(公告)日：2005-03-22
申请号：US10225828
申请日：2002-08-22
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/302 , H01L21/461 , H01L21/764
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

47. 发明授权

US06861317B1 Method of making direct contact on gate by using dielectric stop layer 失效
标题翻译：通过使用介电阻挡层在栅极上直接接触的方法
公开(公告)号：US06861317B1
公开(公告)日：2005-03-01
申请号：US10664211
申请日：2003-09-17
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（fmax）和减小的栅极延迟。

48. 发明授权

US06188135B1 Copper interconnect with top barrier layer 有权
标题翻译：铜互连与顶部阻挡层
公开(公告)号：US06188135B1
公开(公告)日：2001-02-13
申请号：US09294047
申请日：1999-04-19
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的结构和方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

49. 发明授权

US6069069A Method for planarizing a low dielectric constant spin-on polymer using nitride etch stop 失效
标题翻译：使用氮化蚀刻停止平面化低介电常数旋涂聚合物的方法
公开(公告)号：US6069069A
公开(公告)日：2000-05-30
申请号：US767009
申请日：1996-12-16
申请人： Simon Yew-Meng Chooi , Jia Zhen Zheng , Lap Chan
发明人： Simon Yew-Meng Chooi , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/4763
CPC分类号： H01L21/31053 , H01L21/31055 , H01L21/3124 , H01L21/3145 , H01L21/316
摘要： A method for preserving the integrity of the underlying metal lines during planarization by inserting a nitride layer as an etch stop in an oxide-nitride-oxide dielectric layer underlying a spin-on polymer is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines wherein a gap is formed between the conducting lines. A first dielectric layer is deposited over the surfaces of the conducting lines wherein the first dielectric layer contains an etch stop layer wherein the gap remains between the conducting lines. A second dielectric layer is deposited overlying the first dielectric layer wherein the gap is filled by the second dielectric layer. The second dielectric layer is etched back so that the second dielectric layer remains only within the gap wherein the etch stop layer preserves the integrity of the underlying conducting lines. A third dielectric layer is deposited over the first and second dielectric layers and planarized. Alternatively, instead of etching back the second dielectric layer, chemical mechanical polishing (CMP) is used to planarize the layer wherein the etch stop acts as a CMP stop. A third dielectric layer is then deposited over the substrate to complete fabrication of the integrated circuit device.
摘要翻译：描述了在平面化期间通过将氮化物层作为蚀刻停留点插入在旋涂聚合物下面的氧化物 - 氮化物 - 氧化物介电层中来保持底层金属线的完整性的方法。半导体器件结构设置在半导体衬底中和半导体衬底上。导电层沉积在半导体器件结构的表面上，并被图案化以形成导线，其中在导线之间形成间隙。第一电介质层沉积在导电线的表面上，其中第一介电层包含蚀刻停止层，其中间隙保留在导线之间。沉积第二介电层，覆盖第一介电层，其中间隙由第二介电层填充。第二介电层被回蚀刻，使得第二电介质层仅保留在间隙内，其中蚀刻停止层保持下面的导电线的完整性。第三电介质层沉积在第一和第二电介质层上并且被平坦化。或者，代替蚀刻回第二介电层，化学机械抛光（CMP）用于平坦化该层，其中蚀刻停止作为CMP停止。然后将第三介电层沉积在衬底上以完成集成电路器件的制造。

50. 发明授权

US07037791B2 Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates 失效
公开(公告)号：US07037791B2
公开(公告)日：2006-05-02
申请号：US10135071
申请日：2002-04-30
申请人： Lay Cheng Choo , James Yong Meng Lee , Lap Chan
发明人： Lay Cheng Choo , James Yong Meng Lee , Lap Chan
IPC分类号： H01L21/336 , G03C5/00 , G03C5/16
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/76895 , H01L21/823481 , Y10S438/949
摘要： In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

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