专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20130285636A1 POWER TRACKING DEVICE AND POWER TRACKING METHOD 有权
标题翻译：电力跟踪装置和电力跟踪方法
公开(公告)号：US20130285636A1
公开(公告)日：2013-10-31
申请号：US13600531
申请日：2012-08-31
申请人： Kuo-Sen KUNG , Chun-Hao Tu , Ren-Hong Jhan , Wei-Cheng Wu , Ya-Zhi Hsiao , Ting-Chun Lin , Jen-Pei Tseng , Yu-Jung Liu , Jiun-Jye Chang
发明人： Kuo-Sen KUNG , Chun-Hao Tu , Ren-Hong Jhan , Wei-Cheng Wu , Ya-Zhi Hsiao , Ting-Chun Lin , Jen-Pei Tseng , Yu-Jung Liu , Jiun-Jye Chang
IPC分类号： G05F5/00
CPC分类号： G05F1/67
摘要： A power tracking device and a power tracking method is disclosed herein. The power tracking device includes a power voltage setting circuit, a switch, a switching signal circuit, and a voltage memory circuit. The switching signal circuit is configured for sending a first control signal to the switch. When the switch receives the first control signal and electrically isolates the power source and the power voltage setting circuit, the voltage memory circuit stores an open circuit voltage of the power source and sends a setting voltage relative to the open circuit voltage, and when the switch receives the first control signal and electrically connects the power source and the power voltage setting circuit, the power voltage setting circuit sets an output voltage of the power source to correspond with the setting voltage.
摘要翻译：本文公开了功率跟踪装置和功率跟踪方法。功率跟踪装置包括电源电压设定电路，开关，开关信号电路和电压存储电路。开关信号电路被配置为向开关发送第一控制信号。当开关接收到第一控制信号并且电隔离电源和电源电压设置电路时，电压存储电路存储电源的开路电压并发送相对于开路电压的设定电压，并且当开关接收第一控制信号并电连接电源和电源电压设定电路，电源电压设定电路将电源的输出电压设定为与设定电压对应。

42. 发明申请

US20130154022A1 CMOS Devices with Metal Gates and Methods for Forming the Same 有权
标题翻译：具有金属门的CMOS器件及其形成方法
公开(公告)号：US20130154022A1
公开(公告)日：2013-06-20
申请号：US13331214
申请日：2011-12-20
申请人： Sheng-Chen Chung , Ming Zhu , Harry-Hak-Lay Chuang , Bao-Ru Young , Wei-Cheng Wu , Chia Ming Liang , Sin-Hua Wu
发明人： Sheng-Chen Chung , Ming Zhu , Harry-Hak-Lay Chuang , Bao-Ru Young , Wei-Cheng Wu , Chia Ming Liang , Sin-Hua Wu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.
摘要翻译：一种方法包括形成PMOS器件。该方法包括在半导体衬底和PMOS区域上形成栅极电介质层，在栅极电介质层和PMOS区域上形成第一含金属层，对PMOS区域中的第一含金属层进行处理使用含氧处理气体，并在第一含金属层和PMOS区域上形成第二含金属层。第二含金属层具有低于硅的中间间隙功函数的功函数。第一含金属层和第二含金属层形成PMOS器件的栅极。

43. 发明申请

US20130120018A1 Test Structure and Method of Testing Electrical Characteristics of Through Vias 有权
公开(公告)号：US20130120018A1
公开(公告)日：2013-05-16
申请号：US13297779
申请日：2011-11-16
申请人： Shang-Yun Hou , Wei-Cheng Wu , Hsien-Pin Hu , Jung Cheng Ko , Shin-Puu Jeng , Chen-Hua Yu , Kim Hong Chen
发明人： Shang-Yun Hou , Wei-Cheng Wu , Hsien-Pin Hu , Jung Cheng Ko , Shin-Puu Jeng , Chen-Hua Yu , Kim Hong Chen
IPC分类号： G01R31/26 , H01L23/48 , H01L21/58
CPC分类号： H05K1/115 , H01L21/76898 , H01L22/14 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/0557 , H01L2224/1147 , H01L2224/13025 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H05K1/0298 , H05K2201/2081 , H01L2924/01082 , H01L2224/05552 , H01L2924/00
摘要： A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

44. 发明申请

US20120305916A1 Interposer Test Structures and Methods 有权
标题翻译：插件测试结构和方法
公开(公告)号：US20120305916A1
公开(公告)日：2012-12-06
申请号：US13198223
申请日：2011-08-04
申请人： Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng
发明人： Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： H01L23/528
CPC分类号： H01L22/32 , G01R1/07378 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/6835 , H01L22/30 , H01L22/34 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/585 , H01L2221/68331 , H01L2224/05001 , H01L2224/05026 , H01L2224/05572 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00 , H01L2224/05124 , H01L2224/05147
摘要： An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
摘要翻译：本公开的实施例是包括插入器的结构。插入器具有沿着插入件的周边延伸的测试结构，并且测试结构的至少一部分处于第一再分配元件中。第一再分配元件位于中介层的衬底的第一表面上。测试结构是中间的并且电耦合到至少两个探针焊盘。

45. 发明申请

US20110241202A1 Dummy Metal Design for Packaging Structures 有权
标题翻译：包装结构的虚拟金属设计
公开(公告)号：US20110241202A1
公开(公告)日：2011-10-06
申请号：US12750468
申请日：2010-03-30
申请人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
发明人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
IPC分类号： H01L23/485
CPC分类号： H01L23/585 , H01L23/552 , H01L23/562 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13147 , H01L2224/13655 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.
摘要翻译：集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上方并接触金属焊盘。金属凸块形成在UBM上并与UBM电连接。在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。

46. 发明授权

US07969193B1 Differential sensing and TSV timing control scheme for 3D-IC 有权
标题翻译：用于3D-IC的差分感测和TSV时序控制方案
公开(公告)号：US07969193B1
公开(公告)日：2011-06-28
申请号：US12830469
申请日：2010-07-06
申请人： Wei-Cheng Wu , Yen-Huei Chen , Meng-Fan Chang
发明人： Wei-Cheng Wu , Yen-Huei Chen , Meng-Fan Chang
IPC分类号： H03K19/0175
CPC分类号： H03K19/0175 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： This disclosure uses a differential sensing and TSV timing control scheme for 3D-IC, which includes a first chip layer of the stacked device having a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal line, a first differential signal driver is coupled to the sensing circuit, horizontally. The Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer. The Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N−2) TSVs to act as dummy loadings. The TSV and (N−2) TSVs penetrate the stacked device from Nth chip layer to first chip layer. The TSV shares same configuration with the (N−2) TSVs. The Nth differential signal driver is vertically coupled to the first differential signal driver through a pair of TSVs and (N−2) pairs of TSVs, vertically. The pair of TSVs and the (N−2) TSVs penetrate the stacked device from the Nth chip layer to the first chip layer. Each of TSV is formed between a first and a second chip layers. Each of TSV is formed between any adjacent two chip layers of the stacked device.
摘要翻译：本公开使用用于3D-IC的差分感测和TSV定时控制方案，其包括具有检测电路的堆叠装置的第一芯片层和水平耦合到检测电路的相对高能力驱动器。感测电路通过水平线耦合到检测电路，第一差分信号驱动器水平地耦合到感测电路。层叠器件的第N芯片层包括形成在第N芯片层上的第N相对高能力驱动器和第N差分信号驱动器。第N相对高能力驱动器通过一个相对低负载TSV和（N-2）TSV垂直耦合到第一相对高能力的驱动器作为虚拟负载。 TSV和（N-2）TSV穿透层叠器件从第N个芯片层到第一个芯片层。 TSV与（N-2）TSV共享相同的配置。第N个差分信号驱动器通过一对TSV和（N-2）对TSV垂直耦合到第一差分信号驱动器。一对TSV和（N-2）TSV从第N个芯片层穿透层叠器件到第一芯片层。每个TSV形成在第一和第二芯片层之间。每个TSV形成在堆叠设备的任何相邻的两个芯片层之间。

47. 发明授权

US07898081B2 MEMS device and method of making the same 有权
标题翻译： MEMS器件及其制作方法
公开(公告)号：US07898081B2
公开(公告)日：2011-03-01
申请号：US12168057
申请日：2008-07-03
申请人： Bang-Chiang Lan , Li-Hsun Ho , Wei-Cheng Wu , Hui-Min Wu , Min Chen , Chien-Hsin Huang , Ming-I Wang
发明人： Bang-Chiang Lan , Li-Hsun Ho , Wei-Cheng Wu , Hui-Min Wu , Min Chen , Chien-Hsin Huang , Ming-I Wang
IPC分类号： H01L23/00 , H02K41/00
CPC分类号： H04R31/00 , H04R2201/003 , Y10T29/49005
摘要： A MEMS device includes a vent hole structure and a MEMS structure disposed on a same side of a substrate. The vent hole structure adjoins the MEMS structure with an etch stop structure therebetween. The MEMS structure includes a chamber, the vent hole structure includes a metal layer having at least a hole thereon as a vent hole to connect the chamber of the MEMS structure through the etch stop structure. Accordingly, the MEMS device has a lateral vent hole. Furthermore, as the vent hole structure and the MEMS structure are disposed on the same side of the substrate, the manufacturing process is convenient and timesaving.
摘要翻译： MEMS器件包括设置在基板的同一侧上的通气孔结构和MEMS结构。通气孔结构与MEMS结构相邻，其间具有蚀刻停止结构。 MEMS结构包括腔室，通气孔结构包括金属层，其上具有至少一个孔，作为通气孔，以通过蚀刻停止结构连接MEMS结构的室。因此，MEMS器件具有侧向通气孔。此外，由于通气孔结构和MEMS结构设置在基板的同一侧，所以制造过程方便且节省时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式