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41. 发明授权

US06892451B2 Method of making an interposer sub-assembly in a printed wiring board 失效
标题翻译：在印刷电路板中制作插入件子组件的方法
公开(公告)号：US06892451B2
公开(公告)日：2005-05-17
申请号：US10361659
申请日：2003-02-10
申请人： William Louis Brodsky , Benson Chan , Michael Anthony Gaynes , Voya Rista Markovich
发明人： William Louis Brodsky , Benson Chan , Michael Anthony Gaynes , Voya Rista Markovich
IPC分类号： H05K3/32 , H05K3/30
CPC分类号： H01R12/523 , H05K3/325 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49165 , Y10T29/49213
摘要： The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.
摘要翻译：描述印刷电路板（PWB）子组件的细节及其制造方法。子组件包括通过多个连接电连接到一个或多个区域阵列器件（例如模块或印刷线路板）的印刷电路板。子组件可以作为原始组件的一部分。子组件可以用作可以容易地替代为故障组件的后市场项目，其中印刷电路板与一个或两个区域阵列器件之间的尺寸空间必须为表面安装的器件提供足够的间隙。

42. 发明授权

US06545226B2 Printed wiring board interposer sub-assembly 有权
标题翻译：印刷电路板插件子组件
公开(公告)号：US06545226B2
公开(公告)日：2003-04-08
申请号：US09871556
申请日：2001-05-31
申请人： William Louis Brodsky , Benson Chan , Michael Anthony Gaynes , Voya Rista Markovich
发明人： William Louis Brodsky , Benson Chan , Michael Anthony Gaynes , Voya Rista Markovich
IPC分类号： H05K111
CPC分类号： H01R12/523 , H05K3/325 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49165 , Y10T29/49213
摘要： The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.
摘要翻译：描述印刷电路板（PWB）子组件的细节及其制造方法。子组件包括通过多个连接电连接到一个或多个区域阵列器件（例如模块或印刷线路板）的印刷电路板。子组件可以作为原始组件的一部分。子组件可以用作可以容易地替代为故障组件的后市场项目，其中印刷电路板与一个或两个区域阵列器件之间的尺寸空间必须为表面安装的器件提供足够的间隙。

43. 发明授权

US06268016B1 Manufacturing computer systems with fine line circuitized substrates 失效
标题翻译：制造具有细线电路化基板的计算机系统
公开(公告)号：US06268016B1
公开(公告)日：2001-07-31
申请号：US08672290
申请日：1996-06-28
申请人： Anilkumar Chinuprasad Bhatt , Roy Harvey Magnuson , Thomas Richard Miller , Voya Rista Markovich , Carlos J. Sambucetti , Stephen Leo Tisdale
发明人： Anilkumar Chinuprasad Bhatt , Roy Harvey Magnuson , Thomas Richard Miller , Voya Rista Markovich , Carlos J. Sambucetti , Stephen Leo Tisdale
IPC分类号： B05D512
CPC分类号： H05K3/181 , C23C18/1632 , C23C18/2086 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01322 , H01L2924/15312 , Y10T29/49126 , Y10T29/49165
摘要： Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension. The copper plating on the photoimagable dielectric is patterned to form an exterior wiring layer which is covered by solder resist with windows over lands around the through holes and surface mount connection pads of the exterior wiring layer to form a high density circuitized substrate. Surface mount components and/or pin in hole components are attached to the circuitized substrate with solder joints between terminals of the components and the lands and/or connection pads to form a high density circuit board assembly. One or more of the circuit board assemblies are mounted in an enclosure with a power supply, CPU, RAM, and I/O means to form an information handling system with increased performance due to shorter signal flight times due to the higher device density.
摘要翻译：通过形成具有电介质表面的基板并将金属箔层压到基板上来制造电路板。图案化金属箔以形成第一布线层。在布线层上方形成永久的光致可变电介质层，并且通过布线层的焊盘和导体上的电介质层形成通孔。通过基板和基板表面形成孔，包括可光成像的电介质，通孔的壁和穿过无电镀铜工艺的通孔的壁。该方法包括接种表面，用含有表面活性剂的第一溶液涂覆表面和在第二溶液中电镀，其中通过根据表面张力的测定确定表面张力和计量表面活性剂添加到第二溶液中来调节表面活性剂的含量。对可光成像电介质上的镀铜进行图案化以形成外部布线层，该外部布线层由通过孔周围的窗口和外部布线层的表面安装连接焊盘覆盖的阻焊剂覆盖，以形成高密度电路化基板。表面安装部件和/或销孔部件通过部件的端子与焊盘和/或连接焊盘之间的焊接点附接到电路化的基板，以形成高密度电路板组件。一个或多个电路板组件安装在具有电源，CPU，RAM和I / O装置的外壳中，由于更高的器件密度，由于更短的信号飞行时间，从而形成具有增加的性能的信息处理系统。

44. 发明授权

US6093335A Method of surface finishes for eliminating surface irregularities and defects 失效
标题翻译：表面处理方法，用于消除表面不规则和缺陷
公开(公告)号：US6093335A
公开(公告)日：2000-07-25
申请号：US974210
申请日：1997-11-20
申请人： Ashwinkumar C. Bhatt , John Christopher Camp , Subahu Dhirubhai Desai , Voya Rista Markovich , Michael Wozniak
发明人： Ashwinkumar C. Bhatt , John Christopher Camp , Subahu Dhirubhai Desai , Voya Rista Markovich , Michael Wozniak
IPC分类号： B24B7/06 , B24B37/04 , B24B41/047 , C23F1/08 , H05K3/06 , H05K3/26 , B44C1/22
CPC分类号： B24B7/06 , B24B37/04 , B24B41/047 , C23F1/08 , H05K3/068 , H05K3/26 , H05K2203/025 , H05K2203/0346 , H05K2203/0353 , H05K2203/1509
摘要： A method for planarizing an exposed metal surface on a substrate is provided in which surface irregularities are eliminated. A photoresist layer is first removed from the substrate. Then a conformal planarizing head is placed in contact with the metal surface while chemical etchant essentially free of abrasives is supplied to an interface between the metal substrate and the planarizing head. The surface is then planarized until it is free of irregularties.
摘要翻译：提供了在基板上平坦化露出的金属表面的方法，其中消除了表面凹凸。首先从基底去除光致抗蚀剂层。然后将保形平面化头与金属表面接触，同时基本上没有磨料的化学蚀刻剂被提供给金属基底和平坦化头之间的界面。然后将表面平坦化，直到其没有不规则。

45. 发明授权

US5709906A Method for conditioning halogenated polymeric materials and structures fabricated therewith 失效
标题翻译：用于调节卤化聚合物材料和用其制造的结构的方法
公开(公告)号：US5709906A
公开(公告)日：1998-01-20
申请号：US490930
申请日：1995-06-16
申请人： Harry Randall Bickford , Peter J. Duke , Elizabeth Foster , Martin Goldberg , Voya Rista Markovich , Linda Matthew , Donald G. McBride , Terrence Robert O'Toole , Stephen Leo Tisdale , Alfred Viehbeck
发明人： Harry Randall Bickford , Peter J. Duke , Elizabeth Foster , Martin Goldberg , Voya Rista Markovich , Linda Matthew , Donald G. McBride , Terrence Robert O'Toole , Stephen Leo Tisdale , Alfred Viehbeck
IPC分类号： C08J3/24 , C23C18/20 , C23C18/28 , C25D5/56 , H05K1/03 , H05K3/18 , H05K3/38 , H05K3/42 , B05D3/04
CPC分类号： H05K3/422 , C23C18/208 , C23C18/2093 , C23C18/30 , C25D5/56 , H05K3/381 , H05K1/034 , H05K3/181 , Y10S428/901 , Y10T428/24273 , Y10T428/24322 , Y10T428/24339 , Y10T428/24802 , Y10T428/3154 , Y10T428/31544 , Y10T428/31678
摘要： A method of treating a halogenated polymeric-containing substrate including exposing at least portions of the halogenated polymeric-containing substrate to a composition containing a reducing agent and an aprotic solvent selected from the group consisting of nitriles, nitro compounds, amides, esters, carbonates, oxides, sulfo compounds and mixtures thereof. The solvent is free of ethers, amines, ammonia. The composition is prepared by reacting a metal with an organic compound selected from the group consisting of polyaryl compounds, aromatic carbonyl containing compounds, aromatic nitriles, and aromatic heterocyclic nitrogen containing compounds in a reaction solvent that does not react with the metal but permits reaction between the metal and the organic compound to thereby provide the reducing agent. The reducing agent is isolated from the reaction solvent to obtain a reaction product as a solid. The reaction product is added to the aprotic solvent. The treated substrate is contacted with a material to promote adhesion of the material to the treated surface.
摘要翻译：一种处理卤化聚合物基质的方法，包括将含卤代聚合物的底物的至少一部分暴露于含有还原剂和非质子溶剂的组合物，所述组合物选自腈，硝基化合物，酰胺，酯，碳酸酯，氧化物，磺基化合物及其混合物。溶剂不含醚，胺，氨。该组合物是通过在不与金属反应的反应溶剂中使金属与选自由聚芳基化合物，含芳族羰基的化合物，芳族腈和含芳族杂环氮的化合物组成的组中的有机化合物反应而制备的，金属和有机化合物，从而提供还原剂。将还原剂从反应溶剂中分离，得到固体的反应产物。将反应产物加入到非质子溶剂中。经处理的基底与材料接触以促进材料粘附到经处理的表面。

46. 发明授权

US5672980A Method and apparatus for testing integrated circuit chips 失效
标题翻译：用于测试集成电路芯片的方法和装置
公开(公告)号：US5672980A
公开(公告)日：1997-09-30
申请号：US602167
申请日：1996-02-15
申请人： Richard Gordon Charlton , George Charles Correia , Mark Andrew Couture , Gary Ray Hill , Kibby Barth Horsford , Anthony Paul Ingraham , Michael David Lowell , Voya Rista Markovich , Gordon Charles Osborne, Jr. , Mark Vincent Pierson
发明人： Richard Gordon Charlton , George Charles Correia , Mark Andrew Couture , Gary Ray Hill , Kibby Barth Horsford , Anthony Paul Ingraham , Michael David Lowell , Voya Rista Markovich , Gordon Charles Osborne, Jr. , Mark Vincent Pierson
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28
CPC分类号： G01R1/0483 , G01R1/07307 , G01R31/2863 , G01R31/2886
摘要： A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.
摘要翻译：公开了一种用于测试半导体芯片的方法和装置。单个半导体芯片具有I / O触点。该装置设置有具有对应于半导体芯片上的触点的触点的插入器。芯片和内插器触点都可以是任何已知的类型，包括金属球，凸块或凸片，或者可以设置有树枝状表面。首先将芯片触点与插入件上的触点进行相对松动的临时接触，然后将大于每芯片接触5克的压缩力施加到芯片上以迫使芯片触头与插入器触点良好地电接触。然后进行芯片的测试。测试可能包括加热芯片以及将信号应用于芯片触点。测试后，芯片从基板上取下。

47. 发明授权

US5672260A Process for selective application of solder to circuit packages 失效
公开(公告)号：US5672260A
公开(公告)日：1997-09-30
申请号：US633322
申请日：1996-04-17
申请人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
发明人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
IPC分类号： C25D5/02 , C25D5/08 , H01L21/48 , H01L21/60 , H05K3/24 , H05K3/34
CPC分类号： H01L24/81 , C25D5/022 , C25D5/08 , H01L21/4825 , H01L21/4853 , H05K3/241 , H05K3/3473 , H01L2224/11849 , H01L2224/119 , H01L2224/81193 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K2203/043 , H05K2203/054
摘要： Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.

48. 发明授权

US5667934A Thermally stable photoimaging composition 失效
标题翻译：热稳定的光成像组合物
公开(公告)号：US5667934A
公开(公告)日：1997-09-16
申请号：US594780
申请日：1990-10-09
申请人： Voya Rista Markovich , Ashit Arvind Mehta , Eugene Roman Skarvinko , David Wei Wang
发明人： Voya Rista Markovich , Ashit Arvind Mehta , Eugene Roman Skarvinko , David Wei Wang
IPC分类号： G03F7/004 , G03F7/023 , G03F7/029 , G03F7/038 , G03F7/30 , H01L21/027 , H01L21/30 , H05K3/06 , H05K3/28 , H05K3/34 , G03C1/725
CPC分类号： G03F7/0047 , H05K3/287
摘要： A thermally stable photoimaging composition and a method of using the same, especially on circuit boards as a solder mask is provided. The composition includes a polymerizable resin or resin system, a cationic photoinitiator, a solvent, and an optically transparent ceramic filler. Preferably, the composition has a coefficient of thermal expansion of about 28-40 ppm/.degree.C., which closely matches the coefficient of thermal expansion of the solder used on the circuit board components.
摘要翻译：提供了一种热稳定的光成像组合物及其使用方法，特别是在作为焊接掩模的电路板上。该组合物包括可聚合树脂或树脂体系，阳离子光引发剂，溶剂和光学透明陶瓷填料。优选地，组合物具有约28-40ppm /℃的热膨胀系数，其与在电路板部件上使用的焊料的热膨胀系数近似匹配。

49. 发明授权

US5665526A Thermally stable photoimaging composition 失效
公开(公告)号：US5665526A
公开(公告)日：1997-09-09
申请号：US471644
申请日：1995-06-06
申请人： Voya Rista Markovich , Ashit Arvind Mehta , Eugene Roman Skarvinko , David Wei Wang
发明人： Voya Rista Markovich , Ashit Arvind Mehta , Eugene Roman Skarvinko , David Wei Wang
IPC分类号： G03F7/004 , G03F7/023 , G03F7/029 , G03F7/038 , G03F7/30 , H01L21/027 , H01L21/30 , H05K3/06 , H05K3/28 , H05K3/34 , G03C5/00 , C08F2/46
CPC分类号： G03F7/0047 , H05K3/287
摘要： A thermally stable photoimaging composition and a method of using the same, especially on circuit boards as a solder mask is provided. The composition includes a polymerizable resin or resin system, a cationic photoinitiator, a solvent, and an optically transparent ceramic filler. Preferably, the composition has a coefficient of thermal expansion of about 28-40 ppm/.degree. C., which closely matches the coefficient of thermal expansion of the solder used on the circuit board components.

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