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1. 发明授权

US06414509B1 Method and apparatus for in-situ testing of integrated circuit chips 失效
标题翻译：用于集成电路芯片现场测试的方法和装置
公开(公告)号：US06414509B1
公开(公告)日：2002-07-02
申请号：US09564652
申请日：2000-05-03
申请人： Anilkumar Chinuprasad Bhatt , Leo Raymond Buda , Robert Douglas Edwards , Paul Joseph Hart , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla , Richard Gerald Murphy , George John Saxenmeyer, Jr. , George Frederick Walker , Bette Jaye Whalen , Richard Stuart Zarr
发明人： Anilkumar Chinuprasad Bhatt , Leo Raymond Buda , Robert Douglas Edwards , Paul Joseph Hart , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla , Richard Gerald Murphy , George John Saxenmeyer, Jr. , George Frederick Walker , Bette Jaye Whalen , Richard Stuart Zarr
IPC分类号： G01R3102
CPC分类号： H01L24/81 , G01R31/2886 , H01L22/20 , H01L24/75 , H01L2224/0401 , H01L2224/05557 , H01L2224/13111 , H01L2224/75 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.
摘要翻译：公开了半导体芯片的测试方法。单个半导体芯片具有I / O，电源和接地触点。在本发明的方法中，提供了一个芯片载体。芯片载体具有对应于半导体芯片上的触点的触点。载体触点具有树枝状表面。芯片触点与芯片载体上的导体焊盘导电接触。测试信号输入矢量被施加到半导体芯片的输入，从半导体芯片恢复输出信号矢量。在测试之后，芯片可以从衬底去除。或者，芯片可以在成功测试之后通过树枝状导体焊盘粘合到衬底上。

2. 发明授权

US06255208B1 Selective wafer-level testing and burn-in 失效
标题翻译：选择性晶圆级测试和老化
公开(公告)号：US06255208B1
公开(公告)日：2001-07-03
申请号：US09236927
申请日：1999-01-25
申请人： William Emmett Bernier , Claude Louis Bertin , Anilkumar Chinuprasad Bhatt , Michael Anthony Gaynes , Erik Leigh Hedberg , Nikhil M. Murdeshwar , Mark Vincent Pierson , William R. Tonti , Paul A. Totta , Joseph John Van Horn , Jerzy Maria Zalesinski
发明人： William Emmett Bernier , Claude Louis Bertin , Anilkumar Chinuprasad Bhatt , Michael Anthony Gaynes , Erik Leigh Hedberg , Nikhil M. Murdeshwar , Mark Vincent Pierson , William R. Tonti , Paul A. Totta , Joseph John Van Horn , Jerzy Maria Zalesinski
IPC分类号： H01L2144
CPC分类号： H01L24/12 , H01L24/11 , H01L24/16 , H01L24/29 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/1134 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13164 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0781 , H01L2924/09701 , H01L2924/14 , H01L2924/15747 , H01L2924/30107 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/3512
摘要： Selective electrical connections between an electronic component and a test substrate are made using an electrical conductive material. The conductive material of the present invention is a dissolvable material, allowing for rework and repair of a wafer at the wafer-level, and retesting at the wafer-level. In addition, the conductive material may also be used in a permanent package, since the conductive material of the present invention provides complete electrical conductivity and connection between the electronic component and the substrate.
摘要翻译：使用导电材料制成电子部件和测试基板之间的选择性电连接。本发明的导电材料是可溶解的材料，允许在晶片级对晶片进行返修和修复，并且在晶片级重新测试。此外，由于本发明的导电材料提供完整的导电性和电子元件与基片之间的连接，导电材料也可用于永久性封装。

3. 发明授权

US5953594A Method of making a circuitized substrate for chip carrier structure 失效
标题翻译：制造用于芯片载体结构的电路化基板的方法
公开(公告)号：US5953594A
公开(公告)日：1999-09-14
申请号：US820995
申请日：1997-03-20
申请人： Anilkumar Chinuprasad Bhatt , Thomas Richard Miller , Allen Frederick Moring , James Paul Walsh
发明人： Anilkumar Chinuprasad Bhatt , Thomas Richard Miller , Allen Frederick Moring , James Paul Walsh
IPC分类号： H01L21/48 , H01L23/13 , H01L23/498 , H05K1/02 , H05K1/18 , H05K3/10 , H05K3/40 , H05K3/42 , H01L21/44
CPC分类号： H05K3/403 , H01L21/481 , H01L21/486 , H01L23/13 , H01L23/49805 , H01L24/49 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49 , H01L2224/854 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H01L2924/15787 , H01L2924/3011 , H05K1/0203 , H05K1/021 , H05K1/182 , H05K2201/09127 , H05K2203/0191 , H05K2203/0264 , H05K2203/0574 , H05K3/0061 , H05K3/108 , H05K3/427
摘要： An improved method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed, and at least one added layer of metallization is then applied to assure an entirely conductive opening between the member's opposing surfaces. The temporary support assures effective support for the dry film photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps. As taught herein, the entire sidewall portions defining the opening previously occupied by the temporary support portion are metallized to provide enhanced electrical characteristics for the finished product.
摘要翻译：制造可用作芯片载体结构的电路化衬底的改进方法。该方法包括提供电介质构件并部分地布置该构件以在其中限定临时支撑部分的步骤。然后可以发生金属化和电路化，随后除去临时支撑部分，然后施加至少一个附加的金属化层，以确保构件相对表面之间的完全导电的开口。临时支撑确保有效地支持用作电路化过程的一部分的干膜光致抗蚀剂。因此，光致抗蚀剂能够以片状形式施加以跨越电介质的相对小的开口而不会下垂，弯曲等，这可能不利地影响随后的处理步骤。如本文所教导的，限定先前由临时支撑部分占据的开口的整个侧壁部分被金属化以提供成品的增强的电特性。

4. 发明授权

US6114019A Circuit board assemblies having filled vias free from bleed-out 失效
标题翻译：电路板组件具有没有渗出的通孔
公开(公告)号：US6114019A
公开(公告)日：2000-09-05
申请号：US33456
申请日：1998-03-02
申请人： Anilkumar Chinuprasad Bhatt , Donald Herman Glatzel , Allen F. Moring , Voya Rista Markovich , Kostas Papathomas , David John Russell
发明人： Anilkumar Chinuprasad Bhatt , Donald Herman Glatzel , Allen F. Moring , Voya Rista Markovich , Kostas Papathomas , David John Russell
IPC分类号： H05K1/11 , H05K3/00 , H05K3/02 , H05K3/24 , H05K3/40 , H05K3/42 , H05K3/46 , B32B3/00
CPC分类号： H05K3/4652 , H05K1/113 , H05K3/4069 , H05K3/4602 , H01L2224/48091 , H01L2224/73204 , H01L2924/12044 , H05K2201/0347 , H05K2201/0355 , H05K2201/092 , H05K2201/0959 , H05K2203/0191 , H05K2203/025 , H05K2203/0278 , H05K2203/0338 , H05K2203/0554 , H05K3/0023 , H05K3/0094 , H05K3/025 , H05K3/246 , H05K3/429 , Y10S428/901 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , Y10T428/24926 , Y10T428/24942 , Y10T428/249996
摘要： A circuit assembly that includes a circuitized substrate having a dielectric interior layer with a first surface and at least one hole therein. A filler material substantially fills the hole within the dielectric interior layer. A first wiring layer is positioned on the first surface of the dielectric interior layer, wherein the first wiring layer substantially covers the hole and assists in retaining the filler material within the hole in the dielectric interior layer. A first dielectric photoresist layer is positioned on the first wiring layer and on the first surface of the dielectric interior layer. The first dielectric photoresist layer also includes at least one hole therein. The filler material also substantially fills the hole within the first dielectric photoresist layer. A second wiring layer is positioned on the first dielectric photoresist layer and includes a plurality of conductive pads as part thereof. At least one external component can be electrically coupled to the conductive pads of the second wiring layer.
摘要翻译：一种电路组件，其包括具有电介质内层的电路化衬底，其具有第一表面和至少一个孔。填充材料基本上填充电介质内层内的孔。第一布线层位于电介质内层的第一表面上，其中第一布线层基本上覆盖孔，并有助于将填料保持在电介质内层的孔内。第一电介质光致抗蚀剂层定位在第一布线层上和电介质内层的第一表面上。第一电介质光致抗蚀剂层还包括至少一个孔。填充材料还基本上填充第一介电光致抗蚀剂层内的孔。第二布线层位于第一电介质光致抗蚀剂层上，并且包括多个导电焊盘作为其一部分。至少一个外部部件可以电耦合到第二布线层的导电焊盘。

5. 发明授权

US06436803B1 Manufacturing computer systems with fine line circuitized substrates 有权
公开(公告)号：US06436803B1
公开(公告)日：2002-08-20
申请号：US09840432
申请日：2001-04-23
申请人： Anilkumar Chinuprasad Bhatt , Roy Harvey Magnuson , Thomas Richard Miller , Voya Rista Markovich , Carlos J. Sambucetti , Stephen Leo Tisdale
发明人： Anilkumar Chinuprasad Bhatt , Roy Harvey Magnuson , Thomas Richard Miller , Voya Rista Markovich , Carlos J. Sambucetti , Stephen Leo Tisdale
IPC分类号： H01L2144
摘要： Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension. The copper plating on the photoimagable dielectric is patterned to form an exterior wiring layer which is covered by solder resist with windows over lands around the through holes and surface mount connection pads of the exterior wiring layer to form a high density circuitized substrate. Surface mount components and/or pin in hole components are attached to the circuitized substrate with solder joints between terminals of the components and the lands and/or connection pads to form a high density circuit board assembly. One or more of the circuit board assemblies are mounted in an enclosure with a power supply, CPU, RAM, and I/O means to form an information handling system with increased performance due to shorter signal flight times due to the higher device density.

6. 发明授权

US06178093B1 Information handling system with circuit assembly having holes filled with filler material 失效
标题翻译：具有电路组件的信息处理系统，其具有填充有填充材料的孔
公开(公告)号：US06178093B1
公开(公告)日：2001-01-23
申请号：US09033617
申请日：1998-03-03
申请人： Anilkumar Chinuprasad Bhatt , Donald Herman Glatzel , Allen F. Moring , Voya Rista Markovich , Kostas Papathomas , David John Russell
发明人： Anilkumar Chinuprasad Bhatt , Donald Herman Glatzel , Allen F. Moring , Voya Rista Markovich , Kostas Papathomas , David John Russell
IPC分类号： H05K111
CPC分类号： H05K3/4652 , H01L2224/48091 , H01L2224/73204 , H01L2924/12044 , H05K1/113 , H05K3/0023 , H05K3/0094 , H05K3/025 , H05K3/246 , H05K3/4069 , H05K3/429 , H05K3/4602 , H05K2201/0347 , H05K2201/0355 , H05K2201/092 , H05K2201/0959 , H05K2203/0191 , H05K2203/025 , H05K2203/0278 , H05K2203/0338 , H05K2203/0554 , Y10S428/901 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , Y10T428/24926 , Y10T428/24942 , Y10T428/249996 , H01L2924/00014 , H01L2924/00
摘要： An information handling system is provided which comprises: a metal enclosure; at least one circuit assembly positioned within said metal enclosure, said circuit assembly including a circuitized substrate having at least one dielectric interior layer including a first surface and at least one hole therein; means for providing electrical power to said circuitized substrate within said metal enclosure; a filler material, wherein said filler material substantially fills said at least one hole within said at least one dielectric interior layer; a first wiring layer positioned on said first surface of said at least one dielectric interior layer, wherein said first wiring layer substantially covers said at least one hole having said filler material therein, said first wiring layer assisting in retaining said filler material within said at least one hole in said at least one dielectric interior layer; a first dielectric photoresist layer positioned on said first wiring layer and on said first surface of said at least one dielectric interior layer, wherein said first dielectric photoresist layer also includes at least one hole therein, said filler material also substantially filling said at least one hole within said first dielectric photoresist layer; a second wiring layer positioned on said first dielectric photoresist layer; wherein said second wiring layer includes a plurality of conductive pads as part thereof; and at least one external component electrically coupled to said conductive pads of said second wiring layer.
摘要翻译：提供了一种信息处理系统，包括：金属外壳; 位于所述金属外壳内的至少一个电路组件，所述电路组件包括具有至少一个电介质内层的电路化基板，其包括第一表面和至少一个孔; 用于向所述金属外壳内的所述电路化基板提供电力的装置; 填充材料，其中所述填充材料基本上填充所述至少一个电介质内层中的所述至少一个孔; 位于所述至少一个电介质内层的所述第一表面上的第一布线层，其中所述第一布线层基本上覆盖其中具有所述填充材料的所述至少一个孔，所述第一布线层有助于将所述填充材料保持在所述至少一个在所述至少一个电介质内层中的一个孔; 位于所述第一布线层和所述至少一个电介质内层的所述第一表面上的第一电介质光致抗蚀剂层，其中所述第一电介质光致抗蚀剂层还包括至少一个孔，所述填充材料还基本上填充所述至少一个孔在所述第一电介质光致抗蚀剂层内; 位于所述第一电介质光致抗蚀剂层上的第二布线层; 其中所述第二布线层包括作为其一部分的多个导电焊盘; 以及电耦合到所述第二布线层的所述导电焊盘的至少一个外部部件。

7. 发明授权

US06110650A Method of making a circuitized substrate 失效
标题翻译：制造电路化基板的方法
公开(公告)号：US06110650A
公开(公告)日：2000-08-29
申请号：US42898
申请日：1998-03-17
申请人： Anilkumar Chinuprasad Bhatt , Thomas Richard Miller , Allen Frederick Moring , James Paul Walsh
发明人： Anilkumar Chinuprasad Bhatt , Thomas Richard Miller , Allen Frederick Moring , James Paul Walsh
IPC分类号： H01L21/48 , H01L23/13 , H01L23/498 , H05K1/02 , H05K1/18 , H05K3/06 , H05K3/10 , H05K3/40 , H05K3/42 , G03F7/00
CPC分类号： H01L23/13 , H01L21/481 , H01L21/486 , H01L23/49805 , H05K3/403 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/01013 , H01L2924/01028 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H05K1/0203 , H05K1/021 , H05K1/182 , H05K2201/09127 , H05K2203/0191 , H05K2203/0264 , H05K3/0061 , H05K3/064 , H05K3/108 , H05K3/427
摘要： A method of making a circuitized substrate wherein a chip-accommodating cavity is formed along with a plurality of conductive elements (e.g., pads, lines, etc.) which form part of the substrate's circuitry. Metallization is facilitated by the use of a photoimageable member that allows for initial removal (peeling) of its sacrificial layer, followed by eventual removal of the photoimaging layer which also forms part of this member. Exposure of the photoimaging layer may occur either through the protective sacrificial layer or subsequent removal thereof.
摘要翻译：一种制造电路化基板的方法，其中与形成基板电路的一部分的多个导电元件（例如，焊盘，线等）一起形成芯片容纳腔。通过使用允许其牺牲层的初始去除（剥离），然后最终去除也成为该部件的一部分的光成像层，可以实现金属化。光成像层的曝光可以通过保护性牺牲层或随后的去除而发生。

8. 发明授权

US5922517A Method of preparing a substrate surface for conformal plating 失效
标题翻译：制备用于保形电镀的基板表面的方法
公开(公告)号：US5922517A
公开(公告)日：1999-07-13
申请号：US662165
申请日：1996-06-12
申请人： Anilkumar Chinuprasad Bhatt , Ashwinkumar C. Bhatt , Voya Rista Markovich , William Earl Wilson , Gerald Walter Jones
发明人： Anilkumar Chinuprasad Bhatt , Ashwinkumar C. Bhatt , Voya Rista Markovich , William Earl Wilson , Gerald Walter Jones
IPC分类号： H05K3/00 , G03F7/095 , H05K3/18 , G03F7/00
CPC分类号： H05K3/184 , G03F7/095
摘要： Bridging between electrically conductive circuit features during conformal plating is prevented by avoiding the deposition of catalytic seed material onto non-circuit areas of the substrate. Preparatory to forming electrical circuit features on a nonconductive substrate by the full additive process, extraneous seed material is either trapped between two layers of a photoimageable film, whereby it is unavailable during plating, or deposited on the surface of an aqueous photoimageable film, which is removed prior to plating. The method embodying the present invention eliminates the need for seed removal after initial plating and prior to conformal plating of a precious metal over the initial plating.
摘要翻译：通过避免催化种子材料沉积到衬底的非电路区域上，防止了在保形电镀过程中导电电路特征之间的桥接。准备通过完全添加的方法在非导电基材上形成电路特征，外来种子材料被捕获在两层可光成像膜之间，由此在电镀期间不可用，或者沉积在水性可光成像膜的表面上，在电镀之前移除。实施本发明的方法消除了在初始镀覆之后以及在初始镀覆之前对贵金属进行适形电镀之前的种子去除的需要。

9. 发明授权

US5905018A Method of preparing a substrate surface for conformal plating 失效
公开(公告)号：US5905018A
公开(公告)日：1999-05-18
申请号：US957275
申请日：1997-10-24
申请人： Anilkumar Chinuprasad Bhatt , Ashwinkumar C. Bhatt , Voya Rista Markovich , William Earl Wilson , Gerald Walter Jones
发明人： Anilkumar Chinuprasad Bhatt , Ashwinkumar C. Bhatt , Voya Rista Markovich , William Earl Wilson , Gerald Walter Jones
IPC分类号： H05K3/00 , G03F7/095 , H05K3/18 , G03F7/20
CPC分类号： H05K3/184 , G03F7/095
摘要： Bridging between electrically conductive circuit features during conformal plating is prevented by avoiding the deposition of catalytic seed material onto non-circuit areas of the substrate. Preparatory to forming electrical circuit features on a nonconductive substrate by the full additive process, extraneous seed material is either trapped between two layers of a photoimageable film, whereby it is unavailable during plating, or deposited on the surface of an aqueous photoimageable film, which is removed prior to plating. The method embodying the present invention eliminates the need for seed removal after initial plating and prior to conformal plating of a precious metal over the initial plating.

10. 发明授权

US06569604B1 Blind via formation in a photoimageable dielectric material 失效
标题翻译：通过在可光成像的电介质材料中形成盲目
公开(公告)号：US06569604B1
公开(公告)日：2003-05-27
申请号：US09345723
申请日：1999-06-30
申请人： Anilkumar Chinuprasad Bhatt , Francis Joseph Downes, Jr. , Robert Lee Lewis , Voya R. Markovich
发明人： Anilkumar Chinuprasad Bhatt , Francis Joseph Downes, Jr. , Robert Lee Lewis , Voya R. Markovich
IPC分类号： G03C500
CPC分类号： H01L23/49816 , H01L23/49827 , H01L2224/16 , H05K3/0023 , H05K3/0035 , H05K3/4602 , H05K2201/09827 , H05K2203/1476
摘要： A blind via structure, and associated laser ablation methods of formation, that includes a blind via within a photoimageable dielectric (PID) layer on a substrate, such that the sidewall of the blind via makes an obtuse angle with the blind end of the blind via. The obtuse-angled sidewall may be formed by executing two processes in sequence. In the first process, photoimaging of the PID layer, with selective exposure to ultraviolet light, results in one or more blind vias having acute-angled sidewalls. The photoimaging cross links the PID material that had been selectively exposed to ultraviolet light such that a subsequent developing step removes PID material not cross linked, or weakly cross linked, to simultaneously form multiple blind vias having different sized openings. In the second process, laser ablation is selectively employed to remove the acute-angled sidewalls from particular blind vias in a way that forms replacement obtuse-angled sidewalls in the laser-ablated blind vias. Alternatively, the first process involving photoimaging may be omitted such that the second step involving laser ablation forms the entire obtuse-angled blind via. The resultant blind via structure includes at least one blind via having an obtuse-angled sidewall, and optionally, at least one blind via having an acute-angled sidewall.
摘要翻译：盲通孔结构和相关联的激光烧蚀消融方法，其包括在衬底上的可光成像电介质（PID）层内的盲通孔，使得盲通孔的侧壁与盲孔的盲端通过钝角。可以通过依次执行两个过程来形成钝角侧壁。在第一个过程中，通过选择性地暴露在紫外线下的PID层的光成像产生一个或多个具有锐角侧壁的盲孔。光学成像将选择性暴露于紫外线的PID材料交叉连接，使得随后的显影步骤除去未交联或弱交联的PID材料，以同时形成具有不同尺寸开口的多个盲孔。在第二过程中，激光烧蚀被选择性地用于在激光烧蚀的盲孔中形成置换钝角侧壁的方式从特定的盲孔中去除锐角侧壁。或者，可以省略涉及光成像的第一过程，使得涉及激光烧蚀的第二步骤形成整个钝角盲孔。所得到的盲通孔结构包括至少一个具有钝角侧壁的盲孔，并且可选地，至少一个具有锐角侧壁的盲孔。

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