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1. 发明授权

US06344234B1 Method for forming reflowed solder ball with low melting point metal cap 失效
标题翻译：用低熔点金属帽形成回流焊球的方法
公开(公告)号：US06344234B1
公开(公告)日：2002-02-05
申请号：US08476475
申请日：1995-06-07
申请人： Hormazdyar Minocher Dalal , Alexis Bitaillou , Kenneth Michael Fallon , Gene Joseph Gaudenzi , Kenneth Robert Herman , Frederic Pierre , Georges Robert
发明人： Hormazdyar Minocher Dalal , Alexis Bitaillou , Kenneth Michael Fallon , Gene Joseph Gaudenzi , Kenneth Robert Herman , Frederic Pierre , Georges Robert
IPC分类号： B05D512
CPC分类号： H01L24/12 , H01L21/4853 , H01L23/49816 , H01L24/11 , H01L2224/0401 , H01L2224/05171 , H01L2224/05184 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05671 , H01L2224/11472 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/136 , H01L2224/13609 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H05K3/3436 , H05K3/3463 , H05K2201/10992 , H05K2203/0435 , Y02P70/613 , Y10T29/49144 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/013
摘要： A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip burn-in, replacement or field repairs.
摘要翻译：公开了一种用于焊接互连的方法和结构，其使用用于将低温芯片附接到任何更高级别的封装衬底的焊球。在使用标准方法形成焊球后，回流焊锡球表面光滑。一层低熔点金属，例如铋，铟或锡，优选纯锡，沉积在焊料球的顶部。这种结构导致即使在多个低温回流循环之后，在随后的低温接合循环中形成的共晶合金也定位到高熔点焊球的顶部。该方法不需要对芯片要连接的基板进行镀锡，这使得该方法成本低廉。还注意到，当温度升高到略高于共熔温度的情况下，结构总是用铜线在接头周围形成液体圆角。这种液体圆角形成导致显着的热疲劳寿命改善以减少界面处的应力; 其次，为了芯片烧录，更换或现场维修的目的，提供了一种便于拆卸芯片的方法。

2. 发明授权

US06259159B1 Reflowed solder ball with low melting point metal cap 失效
标题翻译：具有低熔点金属帽的回流焊球
公开(公告)号：US06259159B1
公开(公告)日：2001-07-10
申请号：US08794982
申请日：1997-01-30
申请人： Hormazdyar Minocher Dalal , Alexis Bitaillou , Kenneth Michael Fallon , Gene Jospeh Gaudenzi , Kenneth Robert Herman , Frederic Pierre , Georges Robert
发明人： Hormazdyar Minocher Dalal , Alexis Bitaillou , Kenneth Michael Fallon , Gene Jospeh Gaudenzi , Kenneth Robert Herman , Frederic Pierre , Georges Robert
IPC分类号： H01L2348
CPC分类号： H01L24/12 , H01L21/0331 , H01L21/4853 , H01L23/49816 , H01L24/11 , H01L2224/0401 , H01L2224/05171 , H01L2224/05184 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05671 , H01L2224/1147 , H01L2224/11472 , H01L2224/11902 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/136 , H01L2224/13609 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H05K3/143 , H05K3/3436 , H05K3/3463 , H05K2201/10992 , H05K2203/043 , Y02P70/613 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2924/00 , H01L2924/013
摘要： A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip burn-in, replacement or field repairs.
摘要翻译：公开了一种用于焊接互连的方法和结构，其使用用于将低温芯片附接到任何更高级别的封装衬底的焊球。在使用标准方法形成焊球后，回流焊锡球表面光滑。一层低熔点金属，例如铋，铟或锡，优选纯锡，沉积在焊料球的顶部。这种结构导致即使在多个低温回流循环之后，在随后的低温接合循环中形成的共晶合金也定位到高熔点焊球的顶部。该方法不需要对芯片要连接的基板进行镀锡，这使得该方法成本低廉。还注意到，当温度升高到略高于共熔温度的情况下，结构总是用铜线在接头周围形成液体圆角。这种液体圆角形成导致显着的热疲劳寿命改善以减少界面处的应力; 其次，为了芯片烧录，更换或现场维修的目的，提供了一种便于拆卸芯片的方法。

3. 发明授权

US5872051A Process for transferring material to semiconductor chip conductive pads using a transfer substrate 失效
标题翻译：使用转印基板将材料转印到半导体芯片导电焊盘的工艺
公开(公告)号：US5872051A
公开(公告)日：1999-02-16
申请号：US510401
申请日：1995-08-02
申请人： Kenneth Michael Fallon , Christian Robert Le Coz , Mark Vincent Pierson
发明人： Kenneth Michael Fallon , Christian Robert Le Coz , Mark Vincent Pierson
IPC分类号： B23K1/00 , H01L21/48 , H01L21/56 , H01L21/60 , H01L23/485 , H01L23/498 , H05K3/32 , H05K3/34 , H01L21/288 , H01L21/58
CPC分类号： H01L24/12 , B23K1/0016 , H01L21/4867 , H01L21/563 , H01L23/49805 , H01L23/49811 , H01L23/49827 , H01L24/11 , H01L24/16 , H01L24/81 , H05K3/3484 , B23K2201/40 , H01L2224/05001 , H01L2224/05027 , H01L2224/05184 , H01L2224/05572 , H01L2224/11003 , H01L2224/1132 , H01L2224/11334 , H01L2224/1182 , H01L2224/1184 , H01L2224/13006 , H01L2224/13011 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/742 , H01L2224/81136 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15787 , H01L2924/16195 , H01L2924/181 , H01L2924/19043 , H01L2924/3511 , H05K2201/035 , H05K2201/10734 , H05K2201/10992 , H05K2203/0113 , H05K2203/0338 , H05K2203/043 , H05K2203/0557 , H05K3/321 , H05K3/3436 , H05K3/3463
摘要： A process within substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate. The process may be used to produce flip chips, ball grid array modules, column grid array modules, circuit boards, and attachment structures of the preceding components including information handling systems.
摘要翻译：衬底内的工艺设有与表面接触或凸块连通的通孔。连接材料糊料被迫通过筛网上的孔到基板上的触点的区域阵列上，然后当膏被加热和冷却以将接合材料转移到触点上时，屏幕被偏压到基板上。或者，将接合材料糊剂强制进入筛网，然后将基板放置在具有与焊膏接触的基板的凸起接触的区域阵列的屏幕上，然后将该浆料加热并冷却以将材料转移到颠簸接合材料可以是焊膏，导电粘合剂糊或瞬态液体粘合膏。衬底可以是半导体芯片衬底，柔性或刚性有机衬底或涂覆以形成电介质表面的金属衬底。此外，基板可以是计算机芯片，芯片载体基板或电路板基板。该过程可用于制造包括信息处理系统的前述组件的倒装芯片，球栅阵列模块，列网格阵列模块，电路板和附接结构。

4. 发明授权

US5656139A Electroplating apparatus 失效
标题翻译：电镀设备
公开(公告)号：US5656139A
公开(公告)日：1997-08-12
申请号：US585819
申请日：1996-01-16
申请人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
发明人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
IPC分类号： C25D5/02 , C25D5/08 , H01L21/48 , H01L21/60 , H05K3/24 , H05K3/34 , C25D17/00 , C25D21/10
CPC分类号： H01L24/81 , C25D5/022 , C25D5/08 , H01L21/4825 , H01L21/4853 , H05K3/241 , H05K3/3473 , H01L2224/11849 , H01L2224/119 , H01L2224/81193 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K2203/043 , H05K2203/054
摘要： Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.
摘要翻译：可以通过在具有孔或凹槽（例如盲孔）的电介质层的表面上沉积导电材料层并且暴露于其中的导体和/或焊盘而形成具有高体积精度和形状均匀性的小的，紧密间隔的焊料材料沉积物孔或凹槽，导电材料的掩模区域和另外的图案化介电层，将电镀焊料材料电镀到由掩模曝光的导电材料的区域上，通过选择性蚀刻和至少从至少有孔电介质层的一部分表面。盲孔内电镀的均匀性通过流体喷射和阴极搅拌的组合增强。在电镀之前，可以通过在浸没池中用焊料材料的构成成分代替导体材料来避免所得到的焊料沉积物中的过多的导体材料。

5. 发明授权

US5650595A Electronic module with multiple solder dams in soldermask window 失效
标题翻译：在焊接窗口中具有多个焊接坝的电子模块
公开(公告)号：US5650595A
公开(公告)日：1997-07-22
申请号：US450441
申请日：1995-05-25
申请人： Mark Rudolf Bentlage , Kenneth Michael Fallon , Lawrence Harold White
发明人： Mark Rudolf Bentlage , Kenneth Michael Fallon , Lawrence Harold White
IPC分类号： H01L21/60 , H01L21/56 , H01L23/12 , H01L23/28 , H01L23/538 , H05K3/24 , H05K3/34 , H05K1/02
CPC分类号： H05K3/3452 , H01L23/5386 , H01L24/16 , H01L2924/01322 , H01L2924/14 , H05K2201/2081 , H05K2203/0315 , H05K3/243
摘要： The present method employs a first plating resist for forming circuit lines on a carrier substrate. While the plating resist is still in place a metal, such as nickel, is deposited on top of the circuit lines. A second plating resist is employed for plating solder on the circuit lines at solder sites. At this stage additional solder can be deposited at each solder site to provide or supplement the necessary low melt solder required for forming a solder joint. The first and second resists along with solder thereon are then stripped and copper foil on the carrier substrate is etched away around the circuit lines. A soldermask is then formed on the carrier substrate over the circuit lines except for circuit lines in the chip sites. The soldermask has a single large opening at each chip site which has lateral dimensions which are slightly larger than the lateral dimensions of the chip to be connected at the chip site. During curing of the soldermask, which involves heat, the nickel layer on top of the circuit lines within the chip site opening quickly oxidizes to provide solder dams which extend along the lengths of the lines within the chip site openings immediately adjacent the solder sites. The chips are then placed within the soldermask windows and electrically connected by solder joints to the solder sites of the circuit lines by a flip chip attach method. The chip sites are then encapsulated with an underfill encapsulant to protect the solder joints.
摘要翻译：本方法采用在载体基板上形成电路线的第一电镀抗蚀剂。当电镀抗蚀剂仍然存在时，诸如镍的金属沉积在电路线的顶部上。使用第二电镀抗蚀剂在焊接点上在电路线上电镀焊料。在这个阶段，可以在每个焊点处沉积额外的焊料，以提供或补充形成焊点所需的必需的低熔点焊料。然后剥离第一和第二抗蚀剂以及其上的焊料，并且在电路线周围蚀刻载体衬底上的铜箔。然后在载体基板上通过芯片位置中的电路线路之外的电路线路形成焊接掩模。焊接掩模在每个芯片位置具有单个大的开口，其具有比在芯片部分处连接的芯片的横向尺寸稍大的横向尺寸。在包括热量的焊接掩模的固化期间，芯片位置开口内的电路线顶部的镍层快速氧化，以提供沿着紧邻焊料位置的芯片位置开口内的线的长度延伸的焊接坝。然后将芯片放置在焊接窗口内，并通过倒装芯片连接方法通过焊接点电连接到电路线路的焊点。然后将芯片位置用底部填充密封剂封装以保护焊点。

6. 发明授权

US06759738B1 Systems interconnected by bumps of joining material 有权
标题翻译：由连接材料的凸块相互连接的系统
公开(公告)号：US06759738B1
公开(公告)日：2004-07-06
申请号：US09250524
申请日：1999-02-16
申请人： Kenneth Michael Fallon , Christian Robert Le Coz , Mark Vincent Pierson
发明人： Kenneth Michael Fallon , Christian Robert Le Coz , Mark Vincent Pierson
IPC分类号： H01L2348
CPC分类号： H01L24/12 , B23K1/0016 , B23K2101/40 , H01L21/4867 , H01L21/563 , H01L23/49805 , H01L23/49811 , H01L23/49827 , H01L24/11 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/05001 , H01L2224/05027 , H01L2224/05184 , H01L2224/05572 , H01L2224/11003 , H01L2224/1132 , H01L2224/11334 , H01L2224/1182 , H01L2224/1184 , H01L2224/13006 , H01L2224/13011 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/742 , H01L2224/81136 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00011 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15787 , H01L2924/16195 , H01L2924/181 , H01L2924/19043 , H01L2924/3511 , H01L2924/3841 , H05K3/321 , H05K3/3436 , H05K3/3463 , H05K3/3484 , H05K2201/035 , H05K2201/10734 , H05K2201/10992 , H05K2203/0113 , H05K2203/0338 , H05K2203/043 , H05K2203/0557 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/29099 , H01L2224/05624 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2924/01004
摘要： A substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate. The process may be used to produce flip chips, ball grid array modules, column grid array modules, circuit boards, and attachment structures of the preceding components including information handling systems.
摘要翻译：衬底设置有与表面接触或凸起连通的通孔。连接材料糊料被迫通过筛网上的孔到基板上的触点的区域阵列上，然后当膏被加热和冷却以将接合材料转移到触点上时，屏幕被偏压到基板上。或者，将接合材料糊剂强制进入筛网，然后将基板放置在具有与焊膏接触的基板的凸起接触的区域阵列的屏幕上，然后将该浆料加热并冷却以将材料转移到颠簸接合材料可以是焊膏，导电粘合剂糊或瞬态液体粘合膏。衬底可以是半导体芯片衬底，柔性或刚性有机衬底或涂覆以形成电介质表面的金属衬底。此外，基板可以是计算机芯片，芯片载体基板或电路板基板。该过程可用于制造包括信息处理系统的前述组件的倒装芯片，球栅阵列模块，列网格阵列模块，电路板和附接结构。

7. 发明授权

US5796591A Direct chip attach circuit card 失效
标题翻译：直接芯片连接电路卡
公开(公告)号：US5796591A
公开(公告)日：1998-08-18
申请号：US476472
申请日：1995-06-07
申请人： Hormazdyar Minocher Dalal , Kenneth Michael Fallon
发明人： Hormazdyar Minocher Dalal , Kenneth Michael Fallon
IPC分类号： H01L21/60 , H01L23/485 , H05K1/14 , H05K3/34 , H01L23/532
CPC分类号： H05K3/3436 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/11 , H01L2224/11822 , H01L2224/13 , H01L2224/13021 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13144 , H01L2224/136 , H01L2224/16111 , H01L2224/16237 , H01L2224/81801 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H05K2201/09472 , H05K2201/09509 , H05K2201/10992 , Y02P70/613
摘要： A structure and a method is disclosed for making a laminated circuit carrier card for the purpose of making a Direct Chip Attached Module (DCAM) with low cost and high reliability. The carrier is made using an organic or an inorganic laminated carrier having at least one surface available for direct chip mount. The chip has at least one solder ball with a cap of low melting point metal. The surface of the carrier has electrical features that are directly connected to the low melting point metal on the solder ball of the chip to form the eutectic and this way the chip is directly attached to the carrier.
摘要翻译：公开了用于制造具有低成本和高可靠性的直接芯片连接模块（DCAM）的层叠电路载体卡的结构和方法。载体使用具有至少一个可用于直接芯片安装的表面的有机或无机层压载体制成。该芯片具有至少一个具有低熔点金属帽的焊球。载体的表面具有与芯片的焊球上的低熔点金属直接相连以形成共晶体的电特征，并且这种芯片直接连接到载体上。

8. 发明授权

US5672260A Process for selective application of solder to circuit packages 失效
公开(公告)号：US5672260A
公开(公告)日：1997-09-30
申请号：US633322
申请日：1996-04-17
申请人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
发明人： Charles Francis Carey , Kenneth Michael Fallon , Voya Rista Markovich , Douglas Oliver Powell , Gary Paul Vlasak , Richard Stuart Zarr
IPC分类号： C25D5/02 , C25D5/08 , H01L21/48 , H01L21/60 , H05K3/24 , H05K3/34
CPC分类号： H01L24/81 , C25D5/022 , C25D5/08 , H01L21/4825 , H01L21/4853 , H05K3/241 , H05K3/3473 , H01L2224/11849 , H01L2224/119 , H01L2224/81193 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K2203/043 , H05K2203/054
摘要： Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.

9. 发明授权

US5923090A Microelectronic package and fabrication thereof 失效
标题翻译：微电子封装及其制造
公开(公告)号：US5923090A
公开(公告)日：1999-07-13
申请号：US848718
申请日：1997-05-19
申请人： Kenneth Michael Fallon , William Hsioh-Lien Ma
发明人： Kenneth Michael Fallon , William Hsioh-Lien Ma
IPC分类号： H01L23/31 , H01L25/065 , H01L23/48
CPC分类号： H01L23/3121 , H01L25/0657 , H01L2224/16145 , H01L2224/45124 , H01L2224/45144 , H01L2224/48227 , H01L2224/48644 , H01L2224/48664 , H01L2224/48744 , H01L2224/48764 , H01L2224/73207 , H01L2224/85444 , H01L2224/85464 , H01L2225/0651 , H01L2225/06513 , H01L2225/06582 , H01L24/45 , H01L24/48 , H01L2924/01013 , H01L2924/01014 , H01L2924/01046 , H01L2924/0105 , H01L2924/01079 , H01L2924/01087 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/181
摘要： An electronic package comprising an integrated circuit chip and a flip chip solder bonded thereto is provided. The integrated circuit chip has circuitry over a major surface thereof and has peripheral wire or tab bond pads surrounding an array of C4 connection pads located over this major surface. A flip chip is solder bonded to the C4 connection pads.
摘要翻译：提供了包括集成电路芯片和与其结合的倒装芯片焊料的电子封装。集成电路芯片在其主表面上具有电路，并且具有围绕位于该主表面上的C4连接焊盘的阵列的外围导线或接头接合焊盘。倒装芯片焊接到C4连接焊盘。

10. 发明授权

US5798285A Method of making electronic module with multiple solder dams in soldermask window 失效
标题翻译：在焊接窗口中制造具有多个焊料坝的电子模块的方法
公开(公告)号：US5798285A
公开(公告)日：1998-08-25
申请号：US806863
申请日：1997-02-27
申请人： Mark Rudolf Bentlage , Kenneth Michael Fallon , Lawrence Harold White
发明人： Mark Rudolf Bentlage , Kenneth Michael Fallon , Lawrence Harold White
IPC分类号： H01L21/60 , H01L21/56 , H01L23/12 , H01L23/28 , H01L23/538 , H05K3/24 , H05K3/34 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H05K3/3452 , H01L23/5386 , H01L24/16 , H01L2924/01322 , H01L2924/14 , H05K2201/2081 , H05K2203/0315 , H05K3/243
摘要： The present method employs a first plating resist for forming circuit lines on a carrier substrate. While the plating resist is still in place a metal, such as nickel, is deposited on top of the circuit lines. A second plating resist is employed for plating solder on the circuit lines at solder sites. At this stage additional solder can be deposited at each solder site to provide or supplement the necessary low melt solder required for forming a solder joint. The first and second resists along with solder thereon are then stripped and copper foil on the carrier substrate is etched away around the circuit lines. A soldermask is then formed on the carrier substrate over the circuit lines except for circuit lines in the chip sites. The soldermask has a single large opening at each chip site which has lateral dimensions which are slightly larger than the lateral dimensions of the chip to be connected at the chip site. During curing of the soldermask, which involves heat, the nickel layer on top of the circuit lines within the chip site opening quickly oxidizes to provide solder dams which extend along the lengths of the lines within the chip site openings immediately adjacent the solder sites. The chips are then placed within the soldermask windows and electrically connected by solder joints to the solder sites of the circuit lines by a flip chip attach method. The chip sites are then encapsulated with an underfill encapsulant to protect the solder joints.
摘要翻译：本方法采用在载体基板上形成电路线的第一电镀抗蚀剂。当电镀抗蚀剂仍然存在时，诸如镍的金属沉积在电路线的顶部上。使用第二电镀抗蚀剂在焊接点上在电路线上电镀焊料。在这个阶段，可以在每个焊点处沉积额外的焊料，以提供或补充形成焊点所需的必需的低熔点焊料。然后剥离第一和第二抗蚀剂以及其上的焊料，并且在电路线周围蚀刻载体衬底上的铜箔。然后在载体基板上通过芯片位置中的电路线路之外的电路线路形成焊接掩模。焊接掩模在每个芯片位置具有单个大的开口，其具有比在芯片部分处连接的芯片的横向尺寸稍大的横向尺寸。在包括热量的焊接掩模的固化期间，芯片位置开口内的电路线顶部的镍层快速氧化，以提供沿着紧邻焊料位置的芯片位置开口内的线的长度延伸的焊接坝。然后将芯片放置在焊接窗口内，并通过倒装芯片连接方法通过焊接点电连接到电路线路的焊点。然后将芯片位置用底部填充密封剂封装以保护焊点。

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