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41. 发明申请

US20090150844A1 CRITICAL PATH SELECTION FOR AT-SPEED TEST 审中-公开
标题翻译：用于速度测试的关键路径选择
公开(公告)号：US20090150844A1
公开(公告)日：2009-06-11
申请号：US11954138
申请日：2007-12-11
申请人： Vikram Iyengar , David E. Lackey , Subbayyan Venkatesan , Chandramouli Visweswariah , Jinjun Xiong
发明人： Vikram Iyengar , David E. Lackey , Subbayyan Venkatesan , Chandramouli Visweswariah , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if logic devices within the potential critical path are shared by less than a predetermined number of critical paths within the set of paths. This evaluating and adding process is repeated for each of the potential critical paths until all of the potential critical paths have been evaluated. Then, the potential critical paths within the set of paths can be output.
摘要翻译：关键路径选择的方法提供了一组最初不包含路径的路径。定时工具用于识别集成电路设计的潜在关键路径。如果潜在的关键路径内的逻辑设备被小于路径集合内预定数量的关键路径共享，则评估每个潜在的关键路径并将潜在的关键路径添加到路径集合。对于每个潜在的关键路径重复该评估和添加过程，直到所有潜在的关键路径都被评估为止。然后，可以输出该组路径内的潜在关键路径。

42. 发明授权

US06792582B1 Concurrent logical and physical construction of voltage islands for mixed supply voltage designs 失效
标题翻译：用于混合电源电压设计的并联电压岛的逻辑和物理构造
公开(公告)号：US06792582B1
公开(公告)日：2004-09-14
申请号：US09713829
申请日：2000-11-15
申请人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.
摘要翻译：公开了电压岛的逻辑和物理结构。半导体芯片设计被划分为“箱”，这是设计的区域。以这种方式，可以将半导体芯片设计“切片”成各种区域，然后将这些区域分配给各种电压电平。每个仓可以被认为是电压岛。设计中的电路可以添加到各个机箱中或从各个机箱中移除，从而增加或减少电路的速度和功率：如果将电路放入分配较高电压的箱体中，速度和功率会增加，速度和功率如果将电路放置在具有较低电压的箱中，则减小。还可以改变箱子的大小和位置。通过迭代这些步骤，可以在满足速度限制和其他标准的同时满足最佳功耗。本发明可应用于诸如退火放置工具的任何放置环境，其通过连续细化设计上的电路的位置并且其中可以中断放置过程以使逻辑的放置变化。

43. 发明授权

US06609228B1 Latch clustering for power optimization 失效
标题翻译：锁存聚类功能优化
公开(公告)号：US06609228B1
公开(公告)日：2003-08-19
申请号：US09713571
申请日：2000-11-15
申请人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
发明人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F2217/78
摘要： A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.
摘要翻译：时钟优化的方法和结构，包括根据时钟信号要求创建时钟馈电电路的初始放置; 识别所述时钟馈送电路的簇，其中每个簇包括与所述簇内的每个时钟馈送电路连接的不同的时钟信号供应装置; 改变时钟馈电电路和时钟信号供应装置之间的引脚连接，以将选定的时钟馈电电路切换到不同的簇，以减少时钟馈送电路和每个集群内的时钟信号供应装置之间的导线长度; 以及在设计约束内调整时钟馈电电路的位置，以进一步减少电线的长度。

44. 发明授权

US06300809B1 Double-edge-triggered flip-flop providing two data transitions per clock cycle 有权
标题翻译：双边沿触发器，每个时钟周期提供两个数据转换
公开(公告)号：US06300809B1
公开(公告)日：2001-10-09
申请号：US09616551
申请日：2000-07-14
申请人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
发明人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
IPC分类号： H03K312
CPC分类号： H03K3/012 , H03K3/037 , H03K3/0375
摘要： An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.
摘要翻译：一种包括用于提供时钟信号的时钟的装置，用于提供时钟信号的延迟版本的装置，具有由延迟的时钟信号的相反极性控制的时钟输入的两个透明锁存器，多路复用器具有（i）由锁存器和（ii）由时钟信号馈送的选择输入，以及用于提供用于选择时钟不活动的锁存器的选择信号的装置。优选地，每个锁存器具有扫描输入栅极和扫描输出栅极，并且第一锁存器的扫描输出被施加到第二锁存器的扫描输入以形成可扫描锁存器对。此外，优选地，该装置还包括用于将数据应用于第一和第二锁存器的数据端口和数据端口处的异或门，由此该装置产生门控时钟信号。还公开了一种操作该装置的方法。

45. 发明授权

US5146460A Logic simulation using a hardware accelerator together with an automated error event isolation and trace facility 失效
标题翻译：使用硬件加速器与自动错误事件隔离和跟踪设备进行逻辑仿真
公开(公告)号：US5146460A
公开(公告)日：1992-09-08
申请号：US481145
申请日：1990-02-16
申请人： Dennis F. Ackerman , David R. Bender , Salina S. Chu , George R. Deibert , Gary G. Hallock , David E. Lackey , Robert G. Sheldon , Thomas A. Stranko
发明人： Dennis F. Ackerman , David R. Bender , Salina S. Chu , George R. Deibert , Gary G. Hallock , David E. Lackey , Robert G. Sheldon , Thomas A. Stranko
IPC分类号： G06F11/25 , G06F11/26 , G06F11/34 , G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F11/34
摘要： Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator is supplied to a software simulator for detailed error analysis and fault tracing. The hardware accelerator may then be restarted where it left off or with a different task. In this way, optimal utilization is made of expensive hardware accelerator resources while nonetheless providing error event isolation and the ability to generate detailed traces of the simulated behavior.

46. 发明授权

US08205124B2 Microcontroller for logic built-in self test (LBIST) 有权
标题翻译：用于逻辑的微控制器内置自检（LBIST）
公开(公告)号：US08205124B2
公开(公告)日：2012-06-19
申请号：US12268583
申请日：2008-11-11
申请人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
发明人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/31727
摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.
摘要翻译：内置自检（BIST）微控制器集成电路，适用于逻辑验证。微控制器包括表示微控制器的分层描述的多个硬件描述语言文件，所述多个硬件描述语言文件包括电路设计元素库，多个库设计电路元件，适于存储唯一定义的输入和输出集合用于启用逻辑BIST的信号，以及适于存储对应于测试时钟的行为轮廓的多个值的多个锁存器。

47. 发明授权

US08117579B2 LSSD compatibility for GSD unified global clock buffers 有权
标题翻译： LSSD兼容GSD统一全局时钟缓冲区
公开(公告)号：US08117579B2
公开(公告)日：2012-02-14
申请号：US12023337
申请日：2008-01-31
申请人： James Douglas Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
发明人： James Douglas Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
IPC分类号： G06F17/50
CPC分类号： G01R31/318594 , G01R31/318552
摘要： A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.
摘要翻译：提供了一种方法，系统和程序，用于使用中间时钟信号和一个或多个第一模式控制信号从一般扫描设计（GSD）时钟缓冲器产生电平敏感扫描设计（LSSD）时钟信号，以产生多个LSSD时钟信号从GSD时钟缓冲器的输出部分接收中间时钟信号和第一模式控制信号，其中GSD时钟缓冲器还被配置为响应于接收到GSD模式产生多个GSD时钟信号，产生来自GSD时钟缓冲器的输入部分的中间时钟信号响应于接收GSD模式信号。

48. 发明申请

US20110066904A1 AVOIDING RACE CONDITIONS AT CLOCK DOMAIN CROSSINGS IN AN EDGE BASED SCAN DESIGN 有权
标题翻译：在基于边缘扫描设计的时钟域交叉处避开条件
公开(公告)号：US20110066904A1
公开(公告)日：2011-03-17
申请号：US12557623
申请日：2009-09-11
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G01R31/28
CPC分类号： G01R31/318594
摘要： A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the computer) by only observing latches that receive signals from sources within the clock domains. The structure, system, and method also unblock the clock inputs to the clock domains (using the computer). While the clock domain inputs are unblocked, the structure, system, and method perform a second timing test only of signals that are transmitted between the clock domains by only observing latches that receive signals from other clock domains.
摘要翻译：一种结构，系统和方法将时钟域的时钟输入（使用计算机）。当时钟域输入被阻塞时，结构，系统和方法仅通过仅观察从时钟域内的源接收信号的锁存器来执行在时钟域（使用计算机）内发送的信号的第一定时测试。结构，系统和方法还可以解除对时钟域的时钟输入（使用计算机）。当时钟域输入被解除阻塞时，结构，系统和方法仅通过仅观察从其它时钟域接收信号的锁存器来执行在时钟域之间传输的信号的第二定时测试。

49. 发明申请

US20110055650A1 Hold Transition Fault Model and Test Generation Method 有权
标题翻译：保持过渡故障模型和测试生成方法
公开(公告)号：US20110055650A1
公开(公告)日：2011-03-03
申请号：US12548977
申请日：2009-08-27
申请人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
发明人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
IPC分类号： G06F11/263 , G01R31/28
CPC分类号： G01R31/318357 , G01R31/318328
摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.
摘要翻译：一种保持故障建模和测试生成的方法。该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。

50. 发明授权

US07721170B2 Apparatus and method for selectively implementing launch off scan capability in at speed testing 失效
标题翻译：用于在速度测试中选择性地实施发射扫描能力的装置和方法
公开(公告)号：US07721170B2
公开(公告)日：2010-05-18
申请号：US11874972
申请日：2007-10-19
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318541
摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.
摘要翻译：一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

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