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1. 发明授权

US08964995B2 Acoustic diagnosis and correction system 有权
标题翻译：声学诊断和矫正系统
公开(公告)号：US08964995B2
公开(公告)日：2015-02-24
申请号：US13607033
申请日：2012-09-07
申请人： John M. Cohn , James R. Kozloski , Clifford A. Pickover , Jinjun Xiong
发明人： John M. Cohn , James R. Kozloski , Clifford A. Pickover , Jinjun Xiong
IPC分类号： H04R29/00 , G06F11/30 , G21C17/00
CPC分类号： H04R29/00 , G07C5/008 , G07C5/0808
摘要： An acoustic monitoring system includes a portable acoustic detection device, a sound analysis device and a confidence level device. The portable acoustic detection device is capable of receiving sound at one or more locations near a sound-producing device. The sound analysis device receives the sound from the portable sound detection device, determines a diagnosis based on a comparison between the sound and pre-recorded sound data, and outputs the diagnosis to the portable acoustic detection device. The sound analysis device also determines a corrective action for inhibiting the sound, which is also output to the portable sound detection device. The confidence level device determines a confidence level of the diagnosis indicating a likelihood that the diagnosis is successfully diagnosed.
摘要翻译：声学监测系统包括便携式声学检测装置，声音分析装置和置信水平装置。便携式声学检测装置能够在声音产生装置附近的一个或多个位置处接收声音。声音分析装置从便携式声音检测装置接收声音，根据声音和预先记录的声音数据之间的比较确定诊断，并将该诊断输出到便携式声音检测装置。声音分析装置还确定还输出到便携式声音检测装置的用于抑制声音的校正动作。置信水平装置确定诊断的置信水平，指示诊断成功诊断的可能性。

2. 发明申请

US20140072125A1 ACOUSTIC DIAGNOSIS AND CORRECTION SYSTEM 有权
标题翻译：声学诊断和校正系统
公开(公告)号：US20140072125A1
公开(公告)日：2014-03-13
申请号：US13607033
申请日：2012-09-07
申请人： John M. Cohn , James R. Kozloski , Clifford A. Pickover , Jinjun Xiong
发明人： John M. Cohn , James R. Kozloski , Clifford A. Pickover , Jinjun Xiong
IPC分类号： H04R29/00
CPC分类号： H04R29/00 , G07C5/008 , G07C5/0808
摘要： An acoustic monitoring system includes a portable acoustic detection device, a sound analysis device and a confidence level device. The portable acoustic detection device is capable of receiving sound at one or more locations near a sound-producing device. The sound analysis device receives the sound from the portable sound detection device, determines a diagnosis based on a comparison between the sound and pre-recorded sound data, and outputs the diagnosis to the portable acoustic detection device. The sound analysis device also determines a corrective action for inhibiting the sound, which is also output to the portable sound detection device. The confidence level device determines a confidence level of the diagnosis indicating a likelihood that the diagnosis is successfully diagnosed.
摘要翻译：声学监测系统包括便携式声学检测装置，声音分析装置和置信度装置。便携式声学检测装置能够在声音产生装置附近的一个或多个位置处接收声音。声音分析装置从便携式声音检测装置接收声音，根据声音和预先记录的声音数据之间的比较确定诊断，并将该诊断输出到便携式声音检测装置。声音分析装置还确定还输出到便携式声音检测装置的用于抑制声音的校正动作。置信水平装置确定诊断的置信水平，指示诊断成功诊断的可能性。

3. 发明授权

US08423328B2 Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and mean 失效
标题翻译：使用统计学上正确的空间插值，随空间非均匀统计学相关性与距离，标准偏差和平均值分配随机变量的方法
公开(公告)号：US08423328B2
公开(公告)日：2013-04-16
申请号：US12570195
申请日：2009-09-30
申请人： John M. Cohn , Ulrich A. Finkler , David J. Hathaway , Jeffrey G. Hemmett , Fook-Luen Heng , Jason D Hibbeler , Gie Lee , Wayne H. Woods, Jr. , Cole E. Zemke
发明人： John M. Cohn , Ulrich A. Finkler , David J. Hathaway , Jeffrey G. Hemmett , Fook-Luen Heng , Jason D Hibbeler , Gie Lee , Wayne H. Woods, Jr. , Cole E. Zemke
IPC分类号： G06F17/17
CPC分类号： G06F17/175
摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.
摘要翻译：用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。

4. 发明授权

US08299609B2 Product chips and die with a feature pattern that contains information relating to the product chip 有权
标题翻译：产品芯片和芯片具有包含与产品芯片有关的信息的特征图案
公开(公告)号：US08299609B2
公开(公告)日：2012-10-30
申请号：US13360055
申请日：2012-01-27
申请人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
发明人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
IPC分类号： H01L23/04
CPC分类号： H01L23/544 , H01L21/76807 , H01L21/76838 , H01L21/76843 , H01L21/78 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54433 , H01L2223/54473 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Product chips and die that include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.
摘要翻译：产品芯片和裸片，其包括形成在后端（BEOL）布线结构的金属化水平中的特征图案。图案中的特征包含与管芯相关的信息，例如包括用于制造管芯的晶片识别的唯一标识符和晶片上的管芯的产品芯片位置。这些特征可以通过穿透到包装的模具中的电磁辐射束的帮助来成像，并且以促进成像的方式由特征的存在而改变。

5. 发明申请

US20120120758A1 METHODS FOR READING A FEATURE PATTERN FROM A PACKAGED DIE 失效
标题翻译：从包装纸上读取特征图案的方法
公开(公告)号：US20120120758A1
公开(公告)日：2012-05-17
申请号：US13359818
申请日：2012-01-27
申请人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
发明人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
IPC分类号： G03B42/06 , G01S15/88
CPC分类号： H01L23/544 , H01L21/76807 , H01L21/76838 , H01L21/76843 , H01L21/78 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54433 , H01L2223/54473 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.
摘要翻译：用于跟踪从晶片分离后的裸片的身份的方法。产品芯片和管芯包括形成在后端（BEOL）布线结构的金属化水平中的特征图案。图案中的特征包含与管芯相关的信息，例如包括用于制造管芯的晶片识别的唯一标识符和晶片上的管芯的产品芯片位置。这些特征可以通过穿透到包装的模具中的电磁辐射束的帮助来成像，并且以促进成像的方式由特征的存在而改变。

6. 发明申请

US20110077916A1 Method of Distributing a Random Variable Using Statistically Correct Spatial Interpolation Continuously With Spatially Inhomogeneous Statistical Correlation Versus Distance, Standard Deviation, and Mean 失效
标题翻译：使用统计学上正确的空间插值分布随机变量的方法与空间不均匀的统计相关性与距离，标准偏差和平均值
公开(公告)号：US20110077916A1
公开(公告)日：2011-03-31
申请号：US12570195
申请日：2009-09-30
申请人： John M Cohn , Ulrich A. Finkler , David J. Hathaway , Jefrey G. Hemmett , Fook-Luen Heng , Jason D. Hibbeler , Gie Lee , Wayne H. Woods, JR. , Cole E. Zemke
发明人： John M Cohn , Ulrich A. Finkler , David J. Hathaway , Jefrey G. Hemmett , Fook-Luen Heng , Jason D. Hibbeler , Gie Lee , Wayne H. Woods, JR. , Cole E. Zemke
IPC分类号： G06F17/10 , G06F17/17 , G06F1/02
CPC分类号： G06F17/175
摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.
摘要翻译：用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。

7. 发明授权

US07669170B2 Circuit layout methodology using via shape process 失效
标题翻译：使用通孔形状过程的电路布局方法
公开(公告)号：US07669170B2
公开(公告)日：2010-02-23
申请号：US11676185
申请日：2007-02-16
申请人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
发明人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
摘要翻译：提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。布局迁移工具可用于修改现有布局，以实施新的网格要求。

8. 发明授权

US07285860B2 Method and structure for defect monitoring of semiconductor devices using power bus wiring grids 失效
标题翻译：使用电力总线布线网格的半导体器件缺陷监测的方法和结构
公开(公告)号：US07285860B2
公开(公告)日：2007-10-23
申请号：US11277663
申请日：2006-03-28
申请人： John M. Cohn , Leah Marie P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah Marie P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： H01L23/48
CPC分类号： G01R31/2884 , G01R31/307 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.
摘要翻译：用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每一个中的第二线对最初与第一金属互连层下面的导电结构电隔离。第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。

9. 发明授权

US07240322B2 Method of adding fabrication monitors to integrated circuit chips 有权
标题翻译：将制造监控器添加到集成电路芯片的方法
公开(公告)号：US07240322B2
公开(公告)日：2007-07-03
申请号：US10907494
申请日：2005-04-04
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

10. 发明授权

US07239167B2 Utilizing clock shield as defect monitor 失效
标题翻译：利用时钟屏蔽作为缺陷监视器
公开(公告)号：US07239167B2
公开(公告)日：2007-07-03
申请号：US11382601
申请日：2006-05-10
申请人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

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