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1. 发明授权

US06792582B1 Concurrent logical and physical construction of voltage islands for mixed supply voltage designs 失效
标题翻译：用于混合电源电压设计的并联电压岛的逻辑和物理构造
公开(公告)号：US06792582B1
公开(公告)日：2004-09-14
申请号：US09713829
申请日：2000-11-15
申请人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.
摘要翻译：公开了电压岛的逻辑和物理结构。半导体芯片设计被划分为“箱”，这是设计的区域。以这种方式，可以将半导体芯片设计“切片”成各种区域，然后将这些区域分配给各种电压电平。每个仓可以被认为是电压岛。设计中的电路可以添加到各个机箱中或从各个机箱中移除，从而增加或减少电路的速度和功率：如果将电路放入分配较高电压的箱体中，速度和功率会增加，速度和功率如果将电路放置在具有较低电压的箱中，则减小。还可以改变箱子的大小和位置。通过迭代这些步骤，可以在满足速度限制和其他标准的同时满足最佳功耗。本发明可应用于诸如退火放置工具的任何放置环境，其通过连续细化设计上的电路的位置并且其中可以中断放置过程以使逻辑的放置变化。

2. 发明授权

US06985004B2 Wiring optimizations for power 失效
公开(公告)号：US06985004B2
公开(公告)日：2006-01-10
申请号：US09781369
申请日：2001-02-12
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： H03K17/16
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

3. 发明授权

US07469395B2 Wiring optimizations for power 有权
标题翻译：电力接线优化
公开(公告)号：US07469395B2
公开(公告)日：2008-12-23
申请号：US11952544
申请日：2007-12-07
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.
摘要翻译：一种用于设计电气布线结构的电气布线结构和计算机系统。电气配线结构包括电线对。线对包括第一线和第二线。第二根电线被预定为三态。线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度线。

4. 发明授权

US07346875B2 Wiring optimizations for power 有权
标题翻译：电力接线优化
公开(公告)号：US07346875B2
公开(公告)日：2008-03-18
申请号：US11176712
申请日：2005-07-07
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.
摘要翻译：电气布线结构及其设计方法。该方法识别具有第一线和第二线的至少一个线对。第二根线已经是三态的，也可以是三态的。线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

5. 发明授权

US06711719B2 Method and apparatus for reducing power consumption in VLSI circuit designs 失效
标题翻译：用于降低VLSI电路设计中的功耗的方法和装置
公开(公告)号：US06711719B2
公开(公告)日：2004-03-23
申请号：US09928573
申请日：2001-08-13
申请人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.
摘要翻译：在集成电路（IC）设计中，功率消耗的分量可以表示为功率=½FCV <2>，其中C是由源单元驱动的负载电容，F是源单元的开关频率，V 是总输出电压摆幅。然而，不是由源单元产生的每个信号值都不需要传播到芯片的每个时钟周期连接到源的所有宿单元。因此，将隔离单元插入到将源单元连接到至少一个宿单元的网络（有线）中，以便当由所述源单元输出的信号从所述源单元输出时，将所述至少一个宿单元和所述网的一部分与所述源单元分离源不需要传播。由于去耦合，与至少一个接收器和净部分相关联的负载电容对于这种信号不被源单元体验。因此，整体IC功耗降低。

6. 发明授权

US06687883B2 System and method for inserting leakage reduction control in logic circuits 有权
标题翻译：用于在逻辑电路中插入泄漏减少控制的系统和方法
公开(公告)号：US06687883B2
公开(公告)日：2004-02-03
申请号：US09750969
申请日：2000-12-28
申请人： John M. Cohn , Alvar A. Dean , David J. Hathaway , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , David J. Hathaway , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152 , Y02D50/20
摘要： A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.
摘要翻译：一种用于减少逻辑网络的泄漏功率的方法，包括以下步骤：使用（可观察性）不关心信息以识别各个网络的“睡眠状态”; 基于概率分析确定至少一个网络，其中通过在“睡眠状态”的至少一部分期间将网络强制为特定值来减少预期功率消耗; 并将所确定的网络强制为所述“睡眠状态”的确定值确定部分。

7. 发明授权

US06609228B1 Latch clustering for power optimization 失效
标题翻译：锁存聚类功能优化
公开(公告)号：US06609228B1
公开(公告)日：2003-08-19
申请号：US09713571
申请日：2000-11-15
申请人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
发明人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F2217/78
摘要： A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.
摘要翻译：时钟优化的方法和结构，包括根据时钟信号要求创建时钟馈电电路的初始放置; 识别所述时钟馈送电路的簇，其中每个簇包括与所述簇内的每个时钟馈送电路连接的不同的时钟信号供应装置; 改变时钟馈电电路和时钟信号供应装置之间的引脚连接，以将选定的时钟馈电电路切换到不同的簇，以减少时钟馈送电路和每个集群内的时钟信号供应装置之间的导线长度; 以及在设计约束内调整时钟馈电电路的位置，以进一步减少电线的长度。

8. 发明授权

US08423328B2 Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and mean 失效
标题翻译：使用统计学上正确的空间插值，随空间非均匀统计学相关性与距离，标准偏差和平均值分配随机变量的方法
公开(公告)号：US08423328B2
公开(公告)日：2013-04-16
申请号：US12570195
申请日：2009-09-30
申请人： John M. Cohn , Ulrich A. Finkler , David J. Hathaway , Jeffrey G. Hemmett , Fook-Luen Heng , Jason D Hibbeler , Gie Lee , Wayne H. Woods, Jr. , Cole E. Zemke
发明人： John M. Cohn , Ulrich A. Finkler , David J. Hathaway , Jeffrey G. Hemmett , Fook-Luen Heng , Jason D Hibbeler , Gie Lee , Wayne H. Woods, Jr. , Cole E. Zemke
IPC分类号： G06F17/17
CPC分类号： G06F17/175
摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.
摘要翻译：用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。

9. 发明申请

US20110077916A1 Method of Distributing a Random Variable Using Statistically Correct Spatial Interpolation Continuously With Spatially Inhomogeneous Statistical Correlation Versus Distance, Standard Deviation, and Mean 失效
标题翻译：使用统计学上正确的空间插值分布随机变量的方法与空间不均匀的统计相关性与距离，标准偏差和平均值
公开(公告)号：US20110077916A1
公开(公告)日：2011-03-31
申请号：US12570195
申请日：2009-09-30
申请人： John M Cohn , Ulrich A. Finkler , David J. Hathaway , Jefrey G. Hemmett , Fook-Luen Heng , Jason D. Hibbeler , Gie Lee , Wayne H. Woods, JR. , Cole E. Zemke
发明人： John M Cohn , Ulrich A. Finkler , David J. Hathaway , Jefrey G. Hemmett , Fook-Luen Heng , Jason D. Hibbeler , Gie Lee , Wayne H. Woods, JR. , Cole E. Zemke
IPC分类号： G06F17/10 , G06F17/17 , G06F1/02
CPC分类号： G06F17/175
摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.
摘要翻译：用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。

10. 发明授权

US06751744B1 Method of integrated circuit design checking using progressive individual network analysis 有权
标题翻译：集成电路设计检查方法采用渐进式单独网络分析
公开(公告)号：US06751744B1
公开(公告)日：2004-06-15
申请号：US09475799
申请日：1999-12-30
申请人： Robert J. Allen , John M. Cohn , David J. Hathaway
发明人： Robert J. Allen , John M. Cohn , David J. Hathaway
IPC分类号： G06F112
CPC分类号： G06F17/504 , G06F2217/78
摘要： A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.
摘要翻译：一种用于检查集成电路设计的方法，包括以下步骤：通过分析网络对施加到网络的信号的灵敏度来计算第一性能参数; 将所述第一性能参数与一个或多个规则进行比较以确定第一通过条件，并响应于所述第一通过条件的传递将所述第一性能参数的值写入网表文件; 随后基于第一网络模型计算第二性能参数，以响应于所述第一通过条件的失败来确定第二通过条件，并响应于所述第二通过条件的通过将所述第二性能参数写入所述网表文件，或公开了响应于所述第二通过条件的失败向网表文件写入错误标志。该方法在每个步骤中决定快速计算参数是否提供足够的设计余量，或者是否需要更准确但更长的计算参数。

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