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41. 发明授权

US06486072B1 System and method to facilitate removal of defects from a substrate 失效
标题翻译：有助于从基底去除缺陷的系统和方法
公开(公告)号：US06486072B1
公开(公告)日：2002-11-26
申请号：US09709974
申请日：2000-11-10
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01L21302
CPC分类号： H01L21/02046
摘要： A system and method are disclosed for facilitating removal of a defect from a substrate. A charge is applied at the surface of substrate, such as in the form of an ionized gas, to weaken attractive forces between the defect and the substrate. As a result of weakening the attractive forces, a suitable defect removal system may be employed to remove the defect.
摘要翻译：公开了一种用于便于从基底去除缺陷的系统和方法。在基板的表面，例如以电离气体的形式施加电荷，以减弱缺陷和基板之间的吸引力。作为吸引力减弱的结果，可以采用合适的缺陷去除系统来去除缺陷。

42. 发明授权

US07001830B2 System and method of pattern recognition and metrology structure for an X-initiative layout design 失效
标题翻译：用于X主动布局设计的模式识别和计量结构的系统和方法
公开(公告)号：US07001830B2
公开(公告)日：2006-02-21
申请号：US10653309
申请日：2003-09-02
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： G03F7/70625 , G03F7/70633 , G03F9/7076 , Y10S438/975
摘要： The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.
摘要翻译：本发明涉及用于提供用于检查晶片的最佳方法的检查方法和系统。该方法和系统包括晶片到标线片对准，层间对准和晶片表面特征检查。通过将对角线添加到现有的对准标记来减小交叉点大小和期望点可以驻留的对应区域来改善晶片到标线阵列对准。通过向现有覆盖目标添加倾斜和/或非线性线段，以类似的方式改善了层间对齐。此外，在多个所需的对角轴中提供晶片表面检查允许更精确的特征测量。

43. 发明授权

US06724476B1 Low defect metrology approach on clean track using integrated metrology 失效
标题翻译：使用综合计量的清洁轨道的低缺陷计量方法
公开(公告)号：US06724476B1
公开(公告)日：2004-04-20
申请号：US10261756
申请日：2002-10-01
申请人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
发明人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
IPC分类号： G01N2100
CPC分类号： G01N21/9501
摘要： One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.
摘要翻译：本发明的一个方面涉及在晶片上形成光致抗蚀剂层之前和之后对晶片上的缺陷进行监测的系统和方法。该系统包括装置制造系统，其包括用于产生装置的一个或多个晶片处理系统部件; 在制造系统内部和轨道上集成的缺陷计量系统，其操作用于在进行光致抗蚀剂处理之前检查晶片的缺陷; 以及用于减少在晶片的前侧和/或后侧检测到的缺陷量的晶片清洁系统。如果缺陷的量已经被充分降低，则晶片的前侧可以涂覆有光致抗蚀剂。随后，可以在保护前侧免受损伤的同时检查和清洁晶片的背面。例如，可以进行热冲击处理来进行晶片的清洁。

44. 发明授权

US06556303B1 Scattered signal collection using strobed technique 有权
标题翻译：使用频闪技术分散信号采集
公开(公告)号：US06556303B1
公开(公告)日：2003-04-29
申请号：US09902366
申请日：2001-07-10
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
IPC分类号： G01B1114
CPC分类号： G01B11/0683 , G01B11/0625 , H01L22/12
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译：本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。本发明涉及使用散射法来以周期性方式分析移动基片上的薄膜来控制薄膜形成过程。与移动基板相关联的配准特征可以与信号系统结合使用，以确定移动基板的位置，由此可以执行移动基板上对应位置的可重复分析。散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。

45. 发明授权

US06663723B1 Vapor drying for cleaning photoresists 失效
标题翻译：用于清洁光致抗蚀剂的蒸气干燥
公开(公告)号：US06663723B1
公开(公告)日：2003-12-16
申请号：US09974276
申请日：2001-10-10
申请人： Michael K. Templeton , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan
发明人： Michael K. Templeton , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan
IPC分类号： B08B500
CPC分类号： G03F7/40 , B08B7/00
摘要： One aspect of the present invention relates to a method of cleaning a patterned photoresist clad structure involving the steps of contacting the patterned photoresist clad structure with an alcohol vapor comprising at least one compound having the Formula ROH, wherein R is a hydrocarbon group comprising from 4 to about 8 carbon atoms; condensing the alcohol vapor on the patterned photoresist clad structure; and removing the condensed alcohol vapor from the patterned photoresist clad structure. Another aspect of the present invention involves the use of an alcohol vapor having a boiling point from about 102° C. to about 175° C. Yet another aspect of the present invention involves the use of an alcohol vapor having a flash point from about 15° C. to about 80° C.
摘要翻译：本发明的一个方面涉及一种清洁图案化光致抗蚀剂包覆结构的方法，该方法包括以下步骤：使图案化的光致抗蚀剂包覆结构与包含至少一种具有式ROH的化合物的醇蒸气接触，其中R是包含4 至约8个碳原子; 在图案化的光致抗蚀剂包层结构上冷凝酒精蒸气; 并从图案化的光致抗蚀剂包覆结构去除冷凝的醇蒸气。本发明的另一方面涉及使用沸点为约102℃至约175℃的醇蒸气。本发明的另一方面涉及使用闪点为约15℃的醇蒸汽 ℃至约80℃

46. 发明授权

US07591902B2 Recirculation and reuse of dummy dispensed resist 有权
标题翻译：虚拟分配抗蚀剂的再循环和再利用
公开(公告)号：US07591902B2
公开(公告)日：2009-09-22
申请号：US11615080
申请日：2006-12-22
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael T. Templeton
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael T. Templeton
IPC分类号： B05B1/28 , B05B15/04 , B05B3/00 , B05C11/00
CPC分类号： H01L21/6715 , B05B15/50 , B05C11/08
摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
摘要翻译：本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。虚拟分配的抗蚀剂返回到被采集的储存器。在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。来自分配头的抗蚀剂的流动在分配头保持抗干燥。通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。

47. 发明授权

US07065737B2 Multi-layer overlay measurement and correction technique for IC manufacturing 失效
标题翻译：用于IC制造的多层覆盖测量和校正技术
公开(公告)号：US07065737B2
公开(公告)日：2006-06-20
申请号：US10790296
申请日：2004-03-01
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G06F17/50 , G03F9/00 , G03C5/00
CPC分类号： G03F7/70633 , G01N21/95607 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.
摘要翻译：公开了一种便于测量和校正晶片多层之间覆盖层的系统。该系统包括覆盖在三层或多层晶片之间的重叠目标，以及确定覆盖目标中存在的重叠误差的测量部件，从而确定晶片的三层或更多层之间的重叠误差。可以提供控制部件来校正相邻层和非相邻层之间的覆盖误差，其中校正至少部分地基于由测量部件获得的测量。

48. 发明授权

US06535288B1 Machine readable code to trigger data collection 有权
标题翻译：触发数据采集的机器可读代码
公开(公告)号：US06535288B1
公开(公告)日：2003-03-18
申请号：US09902351
申请日：2001-07-10
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
IPC分类号： G01N2189
CPC分类号： H01L21/67253 , C23C14/547 , C23C16/52 , G01N21/47 , G01N21/9501 , H01L22/26
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate comprising an optical indicia and a periodic analysis structure in a periodic manner. The optical indicia is spatially associated with the periodic analysis structure and is utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译：本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。本发明涉及使用散射法来通过以周期性方式分析包括光学标记和周期性分析结构的移动衬底上的薄膜来控制薄膜形成过程。光学标记在空间上与周期性分析结构相关联，并且与信号系统结合使用以确定移动的衬底的位置，由此可以执行移动衬底上相应位置的可重复分析。散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。

49. 发明授权

US06339955B1 Thickness measurement using AFM for next generation lithography 失效
标题翻译：厚度测量采用AFM进行下一代光刻
公开(公告)号：US06339955B1
公开(公告)日：2002-01-22
申请号：US09540251
申请日：2000-03-31
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G01B528
CPC分类号： G01B21/18 , G01B7/066 , G01B21/08 , G01Q30/04 , G01Q80/00 , H01L22/12 , Y10S977/852
摘要： The present invention relates to a method of determining a film thickness and comprises identifying a depth associated with a defect in an underlying material and forming the film over the underlying material. The method further comprises identifying a depth associated with the defect in the film and then using the identified depths to determine the film thickness. The present invention also relates to a system for determining a film thickness and comprises a defect inspection tool operable to identify a location of one or more defects in an underlying material and a topology measurement tool operable to measure a change in topology of a surface. The system also comprises a controller operably coupled to the defect inspection tool and the topology measurement tool. The controller is adapted to receive location information from the defect inspection tool relating to the one or more defects and use the location information to generate and transmit one or more control signals to the topology measurement tool to evaluate a topology of an underlying material and a film at the location corresponding to the one or more defect to thereby generate topology information. Lastly, the controller is adapted to receive the topology information form the topology measurement tool and determine a film thickness using the topology information.
摘要翻译：本发明涉及一种确定膜厚度的方法，包括确定与下层材料中的缺陷有关的深度并在下面的材料上形成薄膜。该方法还包括识别与薄膜中的缺陷相关联的深度，然后使用所识别的深度来确定膜厚度。本发明还涉及一种用于确定膜厚度的系统，并且包括可操作以识别下层材料中的一个或多个缺陷的位置的缺陷检查工具和可操作以测量表面拓扑变化的拓扑测量工具。该系统还包括可操作地耦合到缺陷检查工具和拓扑测量工具的控制器。所述控制器适于接收来自所述缺陷检查工具的与所述一个或多个缺陷有关的位置信息，并使用所述位置信息来生成并发送一个或多个控制信号到所述拓扑测量工具以评估下面的材料和电影的拓扑在与一个或多个缺陷相对应的位置处，从而生成拓扑信息。最后，控制器适于从拓扑测量工具接收拓扑信息，并使用拓扑信息确定膜厚度。

50. 发明授权

US08028531B2 Mitigating heat in an integrated circuit 有权
标题翻译：减轻集成电路中的热量
公开(公告)号：US08028531B2
公开(公告)日：2011-10-04
申请号：US12537135
申请日：2009-08-06
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： F25B21/02
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.
摘要翻译：本发明提供一种通过采用具有热结构网工作组件的热调节装置来调节和监测集成电路的散热的系统和方法。每个热结构可以用作导热通道，用于将热量从集成电路引入和/或散热，从而在半导体主体上产生更均匀的温度梯度。

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