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41. 发明申请

US20090110898A1 HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE 有权
标题翻译：使用热退火衬底的高电阻SOI衬底波形
公开(公告)号：US20090110898A1
公开(公告)日：2009-04-30
申请号：US11931371
申请日：2007-10-31
申请人： Max Levy , Dale Martin , Gerd Pfeiffer , James A. Slinkman
发明人： Max Levy , Dale Martin , Gerd Pfeiffer , James A. Slinkman
IPC分类号： H01L21/30 , B32B7/02 , B32B9/00 , B32B9/04
CPC分类号： H01L21/76254 , H01L21/76256 , H01L29/78603 , Y10T428/249921 , Y10T428/31504
摘要： A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.
摘要翻译：提供一种使用热退火工艺形成绝缘体上半导体（SOI）衬底的方法，以提供具有位于与掩埋绝缘层的界面处的薄的高电阻率表面层的半导体基底晶片。具体地，本发明的方法制造具有至少部分由掩埋绝缘层分离的SOI层和半导体基底晶片的绝缘体上半导体（SOI）衬底，其中半导体基底晶片包括高电阻率（HR）表层，并且所述HR表面层与所述掩埋绝缘层形成界面。

42. 发明授权

US07355680B2 Method for adjusting lithographic mask flatness using thermally induced pellicle stress 有权
标题翻译：使用热诱导防护薄膜应力调整光刻胶片平整度的方法
公开(公告)号：US07355680B2
公开(公告)日：2008-04-08
申请号：US10905453
申请日：2005-01-05
申请人： Emily F. Gallagher , Louis M. Kindt , James A. Slinkman , Richard E. Wistrom
发明人： Emily F. Gallagher , Louis M. Kindt , James A. Slinkman , Richard E. Wistrom
IPC分类号： G03B27/62 , G03F9/00
CPC分类号： G03F1/64 , G03F1/60
摘要： A method for adjusting the flatness of a lithographic mask includes determining an initial mask flatness of the mask, determining an applied stress for bringing the mask to a desired mask flatness, and determining a mounting temperature of a pellicle frame to be mounted to the mask, the mounting temperature corresponding to the applied stress. The actual temperature of the pellicle frame is adjusted to the determined mounting temperature.
摘要翻译：调整光刻掩模的平坦度的方法包括：确定掩模的初始掩模平坦度，确定施加的应力以使掩模达到期望的掩模平坦度，以及确定要安装到掩模的防护薄膜组件框架的安装温度，安装温度对应于施加的应力。将防护膜框架的实际温度调整到确定的安装温度。

43. 发明授权

US06887798B2 STI stress modification by nitrogen plasma treatment for improving performance in small width devices 失效
标题翻译：通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能
公开(公告)号：US06887798B2
公开(公告)日：2005-05-03
申请号：US10250047
申请日：2003-05-30
申请人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
发明人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
IPC分类号： H01L21/318 , H01L21/762 , H01L29/10 , H01L21/31 , H01L21/469
CPC分类号： H01L29/7842 , H01L21/3185 , H01L21/76237 , H01L29/1033
摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.
摘要翻译：一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。在另一个实施例中，等离子体氮化处理发生在沟槽填充之后。在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。

44. 发明授权

US06875685B1 Method of forming gas dielectric with support structure 失效
标题翻译：用支撑结构形成气体电介质的方法
公开(公告)号：US06875685B1
公开(公告)日：2005-04-05
申请号：US10605766
申请日：2003-10-24
申请人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit , James A. Slinkman
发明人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit , James A. Slinkman
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L29/40
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wing-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.
摘要翻译：在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。在翼层电介质中形成诸如通孔或互连的导电结构。然后形成连接到导电结构的支撑件，支撑件包括其下的区域。然后从该区域去除布线层电介质以形成气体电介质。

45. 发明授权

US06198300B1 Silicided silicon microtips for scanning probe microscopy 失效
标题翻译：硅化硅微尖头用于扫描探针显微镜
公开(公告)号：US06198300B1
公开(公告)日：2001-03-06
申请号：US09436122
申请日：1999-11-08
申请人： Lambert A. Doezema , Philip V. Kaszuba , Leon Moszkowicz , James M. Never , James A. Slinkman
发明人： Lambert A. Doezema , Philip V. Kaszuba , Leon Moszkowicz , James M. Never , James A. Slinkman
IPC分类号： G01R3102
CPC分类号： G01Q60/40 , G01Q60/30 , Y10S977/879
摘要： A micromechanical sensor probe for a scanned-probe tool includes a silicon cantilever and a silicon tip physically attached to the cantilever. The micromechanical sensor probe has a coating of a refractory metal silicide formed at least on the tip. Titanium silicide is preferred. The probe also has a layer of refractory metal nitride formed entirely over the refractory metal silicide.
摘要翻译：用于扫描探针工具的微机械传感器探针包括物理连接到悬臂的硅悬臂和硅尖端。微机械传感器探针具有至少形成在尖端上的难熔金属硅化物的涂层。硅化钛是优选的。该探针还具有完全覆盖在难熔金属硅化物上的难熔金属氮化物层。

46. 发明授权

US6101519A Method for efficiently determining a fermi-dirac integrals 失效
标题翻译：有效确定费米尔 - 迪拉克积分的方法
公开(公告)号：US6101519A
公开(公告)日：2000-08-08
申请号：US98909
申请日：1998-06-17
申请人： James A. Slinkman
发明人： James A. Slinkman
IPC分类号： G06F17/10 , G06F7/38
CPC分类号： G06F17/10
摘要： A computer implemented method for efficiently evaluating a Fourier sine/cosine transform of a bounded analytical function is described. The transform is computed in a plurality of steps which reduces the required transform to a sum of two terms which can be efficiently evaluated using a digital computer. The computer evaluates the first and second terms as definite integrals. The first integral is evaluated via standard techniques, and the second integral is evaluated as a definite integral of a sum of terms which converges. The method is advantageously used to provide a model of semiconductor devices which takes into account quantum mechanical effects while minimizing compute operation time. A look-up table of semiconductor carrier density versus spatially dependent field values can optionally be constructed.
摘要翻译：描述了一种用于有效评估有界分析函数的傅里叶正弦/余弦变换的计算机实现方法。在多个步骤中计算变换，其将所需变换减少到可以使用数字计算机有效评估的两个项的和。计算机将第一和第二项评估为定积分。第一个积分通过标准技术进行评估，第二个积分被评估为收敛的项的总和的一个积分。该方法有利地用于提供在最小化计算操作时间的同时考虑量子力学效应的半导体器件的模型。可以可选地构建半导体载流子密度与空间依赖场值的查找表。

47. 发明授权

US07812347B2 Integrated circuit and methods of measurement and preparation of measurement structure 失效
标题翻译：集成电路及测量方法及测量结构的准备
公开(公告)号：US07812347B2
公开(公告)日：2010-10-12
申请号：US12044030
申请日：2008-03-07
申请人： George W. Banke, Jr. , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
发明人： George W. Banke, Jr. , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
IPC分类号： H01L23/58
CPC分类号： A61M1/0058 , A61M1/0084 , G01N1/32 , G01R31/2898
摘要： A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
摘要翻译：通过测量结构的印记来测量集成电路（IC）结构的方法，制备用于上述测量的测试部位的方法和如此形成的IC。用于制备测试部位的方法包括从衬底逐渐去除结构，以便在衬底的顶表面中露出结构的去除的底表面的印记。然后可以使用原子力显微镜（AFM）对印记进行成像。该图像可用于测量结构的底面。

48. 发明授权

US07442996B2 Structure and method for enhanced triple well latchup robustness 有权
标题翻译：增强三井闭锁鲁棒性的结构和方法
公开(公告)号：US07442996B2
公开(公告)日：2008-10-28
申请号：US11275644
申请日：2006-01-20
申请人： David S. Collins , James A. Slinkman , Steven H. Voldman
发明人： David S. Collins , James A. Slinkman , Steven H. Voldman
IPC分类号： H01L29/76
CPC分类号： H01L27/0928 , H01L21/761 , H01L27/0921 , H01L29/1087
摘要： Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.
摘要翻译：公开了一种三阱CMOS器件结构，其通过在p阱下面添加n +掩埋层来解决闭锁的问题，以将p阱与p-衬底隔离，但也在n阱下方。该结构通过将n +掩埋层延伸到整个器件的下方来消除n阱和n +掩埋层之间的间隔问题。该结构还通过在n +掩埋层下方的整个器件下方或仅在器件的p阱侧下面的p +掩埋层提供阈值电压散射的问题，仅在n +掩埋层之下或之上）锁存稳健性可以进一步通过将在n +掩埋层和n阱之间消除侧向pnp，npn或pnpn器件和/或子集电极区域的隔离结构结合到器件中来改进。

49. 发明授权

US06946376B2 Symmetric device with contacts self aligned to gate 失效
标题翻译：触点自对准的对称装置
公开(公告)号：US06946376B2
公开(公告)日：2005-09-20
申请号：US10173950
申请日：2002-06-17
申请人： Juan A. Chediak , Randy W. Mann , James A. Slinkman
发明人： Juan A. Chediak , Randy W. Mann , James A. Slinkman
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76838 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a surface of the semiconductor substrate, a conductive gate aligned on the gate dielectric, a silicide layer aligned on the conductive gate, and a silicon nitride cap aligned on the silicide layer. Insulative spacers are formed on sidewalls of the gate structure, and the insulative spacers contact the semiconductor substrate. A drain region and a source region are formed within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate structure is over the channel region. After an insulative region containing a photosensitive material, such as boro-phoso-silicate glass, is formed over the gate structure and the semiconductor substrate, a cavity over the drain region and a cavity over the source region are formed photolithographically. The cavities are filled with conductive material such as tungsten, forming a conductive contact to the drain region and a conductive contact to the source region. The top surfaces of the conductive contacts and the top surface of the gate structure are coplanar.
摘要翻译：在诸如场效应晶体管（FET）的半导体器件的漏极和源极区域中形成导电接触的方法。栅极结构形成在半导体衬底的一部分上，其中栅极结构包括：在半导体衬底的表面上的栅极电介质，在栅极电介质上对准的导电栅极，在导电栅极上对准的硅化物层，以及在硅化物层上对准氮化硅盖。绝缘垫片形成在栅极结构的侧壁上，并且绝缘垫片与半导体衬底接触。漏极区域和源极区域形成在半导体衬底内，其中沟道区域设置在漏极区域和源极区域之间，并且其中栅极结构在沟道区域之上。在栅极结构和半导体衬底之上形成含有光敏材料（例如硼硅酸盐玻璃）的绝缘区域之后，光刻地形成在漏极区域上方的空腔和源极区域上的空腔。空穴填充有诸如钨的导电材料，形成与漏极区域的导电接触以及与源极区域的导电接触。导电触点的顶表面和栅极结构的顶表面是共面的。

50. 发明授权

US06552411B2 DC or AC electric field assisted anneal 失效
标题翻译： DC或AC电场辅助退火
公开(公告)号：US06552411B2
公开(公告)日：2003-04-22
申请号：US09809887
申请日：2001-03-16
申请人： Arne W. Ballantine , John J. Ellis-Monaghan , Toshihura Furukawa , Jeffrey D. Gilbert , Glenn R. Miller , James A. Slinkman
发明人： Arne W. Ballantine , John J. Ellis-Monaghan , Toshihura Furukawa , Jeffrey D. Gilbert , Glenn R. Miller , James A. Slinkman
IPC分类号： H01L2900
CPC分类号： H01L21/324 , H01L21/2253 , H01L21/26513 , H01L21/326
摘要： A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.
摘要翻译：一种用于在半导体器件中形成期望的接合剖面的方法。将至少一种掺杂剂引入到半导体衬底中。所述至少一种掺杂剂通过对所述半导体衬底和所述至少一种掺杂物退火而在所述半导体衬底中扩散，同时将所述半导体衬底暴露于电场。

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