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1. 发明授权

US06198300B1 Silicided silicon microtips for scanning probe microscopy 失效
标题翻译：硅化硅微尖头用于扫描探针显微镜
公开(公告)号：US06198300B1
公开(公告)日：2001-03-06
申请号：US09436122
申请日：1999-11-08
申请人： Lambert A. Doezema , Philip V. Kaszuba , Leon Moszkowicz , James M. Never , James A. Slinkman
发明人： Lambert A. Doezema , Philip V. Kaszuba , Leon Moszkowicz , James M. Never , James A. Slinkman
IPC分类号： G01R3102
CPC分类号： G01Q60/40 , G01Q60/30 , Y10S977/879
摘要： A micromechanical sensor probe for a scanned-probe tool includes a silicon cantilever and a silicon tip physically attached to the cantilever. The micromechanical sensor probe has a coating of a refractory metal silicide formed at least on the tip. Titanium silicide is preferred. The probe also has a layer of refractory metal nitride formed entirely over the refractory metal silicide.
摘要翻译：用于扫描探针工具的微机械传感器探针包括物理连接到悬臂的硅悬臂和硅尖端。微机械传感器探针具有至少形成在尖端上的难熔金属硅化物的涂层。硅化钛是优选的。该探针还具有完全覆盖在难熔金属硅化物上的难熔金属氮化物层。

2. 发明授权

US6139759A Method of manufacturing silicided silicon microtips for scanning probe microscopy 失效
标题翻译：制造用于扫描探针显微镜的硅化硅微尖头的方法
公开(公告)号：US6139759A
公开(公告)日：2000-10-31
申请号：US256261
申请日：1999-02-23
申请人： Lambert A. Doezema , Philip V. Kaszuba , Leon Moszkowicz , James M. Never , James A. Slinkman
发明人： Lambert A. Doezema , Philip V. Kaszuba , Leon Moszkowicz , James M. Never , James A. Slinkman
IPC分类号： C25F3/08 , G01B7/34 , G01R31/02
CPC分类号： G01Q60/40 , B82Y35/00 , G01Q60/30 , Y10S977/879
摘要： A micromechanical sensor probe for a scanned-probe tool comprising a silicon probe and a coating of a refractory metal silicide formed at least on the tip of the probe. Titanium silicide is preferred. A method for manufacturing such a probe includes the steps of, first, providing a silicon cantilever and tip combination and, second, forming a refractory metal silicide on at least the tip of the cantilever and tip combination. This second step of the method includes removing any remnant oxide from the tip, stabilizing the cantilever and tip combination on a carrier, depositing a refractory metal on the silicon tip, heating the cantilever and tip combination in an ambient free of oxygen to react chemically the refractory metal on and the silicon of the tip, selectively etching any unreacted refractory metal from the tip, and annealing the cantilever and tip combination in an ambient free of oxygen. The method may also include, as a final step, removing any unreacted refractory metal from the tip.
摘要翻译：一种用于扫描探针工具的微机械传感器探针，其包括硅探针和至少形成在探针尖端上的难熔金属硅化物的涂层。硅化钛是优选的。用于制造这种探针的方法包括以下步骤：首先提供硅悬臂和尖端组合，其次，在悬臂和尖端组合的至少尖端上形成难熔金属硅化物。该方法的第二步骤包括从尖端去除任何残余氧化物，将悬臂和尖端组合稳定在载体上，将难熔金属沉积在硅尖端上，在不含氧的环境中加热悬臂和尖端组合以化学反应难熔金属和尖端的硅，从尖端选择性地蚀刻任何未反应的难熔金属，并且在没有氧的环境中退火悬臂和尖端组合。作为最后的步骤，还可以包括从尖端去除任何未反应的难熔金属。

3. 发明申请

US20080157077A1 Integrated Circuit and Methods of Measurement And Preparation of Measurement Structure 失效
标题翻译：集成电路和测量结构的制备方法
公开(公告)号：US20080157077A1
公开(公告)日：2008-07-03
申请号：US12044030
申请日：2008-03-07
申请人： G. W. Banke , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
发明人： G. W. Banke , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
IPC分类号： H01L21/66
CPC分类号： A61M1/0058 , A61M1/0084 , G01N1/32 , G01R31/2898
摘要： A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
摘要翻译：通过测量结构的印记来测量集成电路（IC）结构的方法，制备用于上述测量的测试部位的方法和如此形成的IC。用于制备测试部位的方法包括从衬底逐渐去除结构，以便在衬底的顶表面中露出结构的去除的底表面的印记。然后可以使用原子力显微镜（AFM）对印记进行成像。该图像可用于测量结构的底面。

4. 发明授权

US07812347B2 Integrated circuit and methods of measurement and preparation of measurement structure 失效
标题翻译：集成电路及测量方法及测量结构的准备
公开(公告)号：US07812347B2
公开(公告)日：2010-10-12
申请号：US12044030
申请日：2008-03-07
申请人： George W. Banke, Jr. , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
发明人： George W. Banke, Jr. , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
IPC分类号： H01L23/58
CPC分类号： A61M1/0058 , A61M1/0084 , G01N1/32 , G01R31/2898
摘要： A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
摘要翻译：通过测量结构的印记来测量集成电路（IC）结构的方法，制备用于上述测量的测试部位的方法和如此形成的IC。用于制备测试部位的方法包括从衬底逐渐去除结构，以便在衬底的顶表面中露出结构的去除的底表面的印记。然后可以使用原子力显微镜（AFM）对印记进行成像。该图像可用于测量结构的底面。

5. 发明申请

US20090219508A1 SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGREATED DEVICES 有权
标题翻译：用于检测集成设备中的局部机械应力的系统和方法
公开(公告)号：US20090219508A1
公开(公告)日：2009-09-03
申请号：US12039830
申请日：2008-02-29
申请人： Lloyd Bumm , Daminda Dahayanaka , Philip V. Kaszuba , Leon Moszkowicz , James A. Slinkman
发明人： Lloyd Bumm , Daminda Dahayanaka , Philip V. Kaszuba , Leon Moszkowicz , James A. Slinkman
IPC分类号： G01B11/16
CPC分类号： G01B21/32 , G01Q60/30
摘要： A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.
摘要翻译：提供了一种在集成器件中检测局部机械应力的方法，所述方法包括：使得能够检测扫描探针器件与集成器件的表面部分之间的光电压差，扫描探针器件被配置为响应于光电压差; 测量所述扫描探针装置响应于所述扫描探针装置与所述集成装置的所述表面部分之间的光电压差的偏转; 以及通过基于所述扫描探针装置的偏转来确定所述集成装置的所述表面部分的局部功函数来计算所述集成装置内的局部应力水平。

6. 发明授权

US07944550B2 System and method for detecting local mechanical stress in integreated devices 有权
标题翻译：用于检测集成设备中局部机械应力的系统和方法
公开(公告)号：US07944550B2
公开(公告)日：2011-05-17
申请号：US12039830
申请日：2008-02-29
申请人： Lloyd Bumm , Daminda Dahayanaka , Philip V. Kaszuba , Leon Moszkowicz , James A. Slinkman
发明人： Lloyd Bumm , Daminda Dahayanaka , Philip V. Kaszuba , Leon Moszkowicz , James A. Slinkman
IPC分类号： G01B11/16
CPC分类号： G01B21/32 , G01Q60/30
摘要： A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.
摘要翻译：提供了一种在集成器件中检测局部机械应力的方法，所述方法包括：使得能够检测扫描探针器件与集成器件的表面部分之间的光电压差，扫描探针器件被配置为响应于光电压差; 测量所述扫描探针装置响应于所述扫描探针装置与所述集成装置的所述表面部分之间的光电压差的偏转; 以及通过基于所述扫描探针装置的偏转来确定所述集成装置的所述表面部分的局部功函数来计算所述集成装置内的局部应力水平。

7. 发明授权

US07507591B2 Methods of measurement and preparation of measurement structure of integrated circuit 失效
标题翻译：集成电路测量结构测量方法
公开(公告)号：US07507591B2
公开(公告)日：2009-03-24
申请号：US11160086
申请日：2005-06-08
申请人： George W. Banke, Jr. , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
发明人： George W. Banke, Jr. , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
IPC分类号： H01L21/00 , G01M19/00
CPC分类号： A61M1/0058 , A61M1/0084 , G01N1/32 , G01R31/2898
摘要： A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
摘要翻译：通过测量结构的印记来测量集成电路（IC）结构的方法，制备用于上述测量的测试部位的方法和如此形成的IC。用于制备测试部位的方法包括从衬底逐渐去除结构，以便在衬底的顶表面中露出结构的去除的底表面的印记。然后可以使用原子力显微镜（AFM）对印记进行成像。该图像可用于测量结构的底面。

8. 发明申请

US20130134518A1 NOBLE GAS IMPLANTATION REGION IN TOP SILICON LAYER OF SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
标题翻译：半导体绝缘体基板的顶层硅层中的气体植入区域
公开(公告)号：US20130134518A1
公开(公告)日：2013-05-30
申请号：US13280681
申请日：2011-11-28
申请人： Alan B. Botula , William F. Clark, JR. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , William F. Clark, JR. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L21/84 , H01L27/1203
摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.
摘要翻译：半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。

9. 发明申请

US20100117122A1 Optimized Device Isolation 有权
标题翻译：优化设备隔离
公开(公告)号：US20100117122A1
公开(公告)日：2010-05-13
申请号：US12269073
申请日：2008-11-12
申请人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St Onge , James A. Slinkman
发明人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St Onge , James A. Slinkman
IPC分类号： H01L27/092 , H01L27/085
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928
摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.
摘要翻译：用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域上方，并在所有p阱区域下方， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。隔离MOSFET的n阱连接到深n波段区域。所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

10. 发明授权

US07479688B2 STI stress modification by nitrogen plasma treatment for improving performance in small width devices 有权
标题翻译：通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能
公开(公告)号：US07479688B2
公开(公告)日：2009-01-20
申请号：US10751831
申请日：2004-01-05
申请人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
发明人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
IPC分类号： H01L29/72
CPC分类号： H01L29/7842 , H01L21/3185 , H01L21/76237 , H01L29/1033
摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.
摘要翻译：一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。在又一实施例中，等离子体氮化处理发生在沟槽填充之后。在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。

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