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41. 发明授权

US07286385B2 Differential and hierarchical sensing for memory circuits 失效
标题翻译：存储电路的差分和分层感测
公开(公告)号：US07286385B2
公开(公告)日：2007-10-23
申请号：US11190542
申请日：2005-07-27
申请人： John Edward Barth, Jr. , Paul C. Parries , William Robert Reohr , Matthew R. Wordeman
发明人： John Edward Barth, Jr. , Paul C. Parries , William Robert Reohr , Matthew R. Wordeman
IPC分类号： G11C5/06 , G11C8/00
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译：存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

42. 发明授权

US07057866B2 System and method for disconnecting a portion of an integrated circuit 失效
公开(公告)号：US07057866B2
公开(公告)日：2006-06-06
申请号：US09929591
申请日：2001-08-14
申请人： Louis L. Hsu , Rajiv V. Joshi , Chorng-Lii Hwang , Toshiaki K. Kirihata , Paul C. Parries
发明人： Louis L. Hsu , Rajiv V. Joshi , Chorng-Lii Hwang , Toshiaki K. Kirihata , Paul C. Parries
IPC分类号： G11C8/00
CPC分类号： G11C5/14 , G11C5/147
摘要： An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.

43. 发明授权

US07046572B2 Low power manager for standby operation of memory system 有权
标题翻译：低功耗管理器用于存储系统的待机操作
公开(公告)号：US07046572B2
公开(公告)日：2006-05-16
申请号：US10250233
申请日：2003-06-16
申请人： David R. Hansen , Gregory J. Fredeman , John W. Golz , Hoki Kim , Paul C. Parries
发明人： David R. Hansen , Gregory J. Fredeman , John W. Golz , Hoki Kim , Paul C. Parries
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C8/08
摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
摘要翻译：存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线司机。具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

44. 发明授权

US06518145B1 Methods to control the threshold voltage of a deep trench corner device 失效
标题翻译：控制深沟槽角设备阈值电压的方法
公开(公告)号：US06518145B1
公开(公告)日：2003-02-11
申请号：US09130226
申请日：1998-08-06
申请人： Johann Alsmeier , George R. Goth , Max G. Levy , Victor R. Nastasi , James A. O'Neill , Paul C. Parries
发明人： Johann Alsmeier , George R. Goth , Max G. Levy , Victor R. Nastasi , James A. O'Neill , Paul C. Parries
IPC分类号： H01L2176
CPC分类号： H01L21/763 , H01L21/823481
摘要： A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the underlying oxide layer, filling the recess with a nitride plug, filling the trench a conductive material and oxidizing the dielectric and the conductive material, wherein the nitride plug controls a shape of a corner of the trench.
摘要翻译：制造半导体沟槽器件的方法包括在衬底上形成电介质，所述电介质具有与衬底相邻的下面的氧化物层，蚀刻电介质和衬底中的沟槽，在下面的氧化物层中形成凹陷，用氮化物塞，将沟槽填充导电材料并氧化电介质和导电材料，其中氮化物塞控制沟槽角部的形状。

45. 发明授权

US06294449B1 Self-aligned contact for closely spaced transistors 失效
标题翻译：紧密间隔晶体管的自对准触点
公开(公告)号：US06294449B1
公开(公告)日：2001-09-25
申请号：US09447627
申请日：1999-11-23
申请人： Teresa J. Wu , Bomy A. Chen , John W. Golz , Charles W. Koburger, III , Paul C. Parries , Christopher J. Waskiewicz , Jin Jwang Wu
发明人： Teresa J. Wu , Bomy A. Chen , John W. Golz , Charles W. Koburger, III , Paul C. Parries , Christopher J. Waskiewicz , Jin Jwang Wu
IPC分类号： H01L2144
CPC分类号： H01L21/76897
摘要： A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.
摘要翻译：一对共用共用电极的晶体管 DRAM阵列中的位线具有与位线的自对准接触，其中晶体管栅极堆叠仅具有具有氮化物覆盖层的多晶硅层; 用于位线接触的孔径被时间刻蚀以仅在栅极之间穿透而不到达硅衬底; 蚀刻栅极的暴露的氮化物肩部以暴露多晶硅; 通过选择性蚀刻去除层间电介质的其余部分; 暴露的聚合物被再氧化以保护浇口; 并清洁孔径底部; 从而不需要DRAM的厚栅堆叠，以便提高跨芯片的线宽的均匀性，超出了DRAM技术可以传送的范围。

46. 发明授权

US06194736B1 Quantum conductive recrystallization barrier layers 失效
标题翻译：量子导电重结晶阻挡层
公开(公告)号：US06194736B1
公开(公告)日：2001-02-27
申请号：US09213674
申请日：1998-12-17
申请人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
发明人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
IPC分类号： H01L2906
CPC分类号： H01L29/66181 , H01L21/02667 , H01L21/2022 , H01L27/10867
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用量子传导重结晶阻挡层，能够实现提高可靠性和/或增加组合选择的缩小结构。量子导电层优选用于沟槽电容器中以用作再结晶屏障。

47. 发明申请

US20110092043A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20110092043A1
公开(公告)日：2011-04-21
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

48. 发明申请

US20090240875A1 CONTENT ADDRESSABLE MEMORY WITH HIDDEN TABLE UPDATE, DESIGN STRUCTURE AND METHOD 审中-公开
标题翻译：内容可寻址存储器，具有隐藏表更新，设计结构和方法
公开(公告)号：US20090240875A1
公开(公告)日：2009-09-24
申请号：US12050340
申请日：2008-03-18
申请人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
发明人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
IPC分类号： G11C15/04 , G11C7/00
CPC分类号： G11C15/043 , G11C11/406
摘要： Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method.
摘要翻译：公开了具有两个分立存储器件的存储器电路的实施例，其具有存储基本上相同的数据库的两个分立存储器阵列。第一设备是适于执行需要读取功能（即，所有更新和刷新操作）的所有维护操作的常规存储器。第二设备是仅适用于执行并行搜索和重写操作的基于DRAM的CAM设备。第二设备的覆盖操作的性能与第一设备的维护操作的性能一起发生，使得两个设备中的相应存储器单元存储基本上相同的数据值。由于存储器件中的数据库基本上相同，并且由于维护和并行搜索操作不由同一设备执行，所以可以不中断地执行并行搜索操作。还公开了相关设计结构和方法的实施例。

49. 发明申请

US20090184356A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20090184356A1
公开(公告)日：2009-07-23
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

50. 发明申请

US20090173980A1 PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR 有权
标题翻译：提供隔离通过深度电容电容器进行字线传输
公开(公告)号：US20090173980A1
公开(公告)日：2009-07-09
申请号：US11969989
申请日：2008-01-07
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Herbert L. Ho , Paul C. Parries
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Herbert L. Ho , Paul C. Parries
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译：存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。衬垫可以是一层氧化物上的氮化物层。一些STI可以覆盖衬垫的一部分。在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。

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