专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08198169B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US08198169B2
公开(公告)日：2012-06-12
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/425
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

2. 发明授权

US07888723B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US07888723B2
公开(公告)日：2011-02-15
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

3. 发明申请

US20110092043A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20110092043A1
公开(公告)日：2011-04-21
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

4. 发明申请

US20090184356A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20090184356A1
公开(公告)日：2009-07-23
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

5. 发明申请

US20090242953A1 SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE 有权
标题翻译：与高K /金属闸门兼容的低压电容器
公开(公告)号：US20090242953A1
公开(公告)日：2009-10-01
申请号：US12059174
申请日：2008-03-31
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/108 , H01L21/8242 , G06F17/50
CPC分类号： H01L27/0629
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

6. 发明授权

US07759766B2 Electrical fuse having a thin fuselink 失效
标题翻译：电熔丝具有薄的熔丝
公开(公告)号：US07759766B2
公开(公告)日：2010-07-20
申请号：US11843047
申请日：2007-08-22
申请人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.
摘要翻译：薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

7. 发明授权

US07875919B2 Shallow trench capacitor compatible with high-K / metal gate 有权
标题翻译：浅沟槽电容器兼容高K /金属门
公开(公告)号：US07875919B2
公开(公告)日：2011-01-25
申请号：US12059174
申请日：2008-03-31
申请人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/108
CPC分类号： H01L27/0629
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

8. 发明授权

US07671394B2 Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode 有权
标题翻译：具有高k节点电介质和金属内电极的嵌入式沟槽电容器
公开(公告)号：US07671394B2
公开(公告)日：2010-03-02
申请号：US11873728
申请日：2007-10-17
申请人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/106 , H01L21/8242
CPC分类号： H01L27/1087
摘要： A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.
摘要翻译：在半导体衬底和衬垫层中形成深沟槽，并填充有虚拟节点电介质和虚设沟槽填充物。在半导体衬底中形成浅沟槽隔离结构。去除焊盘层之后，在器件区域中形成虚拟栅极结构。在虚拟栅极结构上形成第一电介质层，并且填充虚拟沟槽的突出部分，然后进行平坦化。虚拟结构被去除。深沟槽和通过去除伪栅极结构形成的空腔填充有高介电常数材料层和金属层，其形成深沟槽中的高k节点电介质和深沟槽电容器的金属内电极以及在器件区域中的高k栅极电介质和金属栅极。

9. 发明申请

US20090101956A1 EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE 有权
标题翻译：具有高K节点电介质和金属内电极的嵌入式电容器
公开(公告)号：US20090101956A1
公开(公告)日：2009-04-23
申请号：US11873728
申请日：2007-10-17
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/108 , H01G4/00 , H01L21/8242
CPC分类号： H01L27/1087
摘要： A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.
摘要翻译：在半导体衬底和衬垫层中形成深沟槽，并填充有虚拟节点电介质和虚设沟槽填充物。在半导体衬底中形成浅沟槽隔离结构。去除焊盘层之后，在器件区域中形成虚拟栅极结构。在虚拟栅极结构上形成第一电介质层，并且填充虚拟沟槽的突出部分，然后进行平坦化。虚拟结构被去除。深沟槽和通过去除伪栅极结构形成的空腔填充有高介电常数材料层和金属层，其形成深沟槽中的高k节点电介质和深沟槽电容器的金属内电极以及在器件区域中的高k栅极电介质和金属栅极。

10. 发明申请

US20090051002A1 ELECTRICAL FUSE HAVING A THIN FUSELINK 失效
标题翻译：电子保险丝
公开(公告)号：US20090051002A1
公开(公告)日：2009-02-26
申请号：US11843047
申请日：2007-08-22
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.
摘要翻译：薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式