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41. 发明授权

US5483706A Flush device for toilet 失效
标题翻译：马桶冲洗装置
公开(公告)号：US5483706A
公开(公告)日：1996-01-16
申请号：US367729
申请日：1995-01-03
申请人： Pang-Yen Tsai , Chien-Liang Hsiao
发明人： Pang-Yen Tsai , Chien-Liang Hsiao
IPC分类号： E03D1/14
CPC分类号： E03D1/144
摘要： A flush device for toilet comprises within a water tank a support arm including a check member, a restricting member and a outlet valve attached in series to an overflow tube, and an actuating assembly including a actuator arm connected with the outlet valve via the support arm by a lift wire or chain. The check member facilitates varying the discharge amount of the flush water and smooth operation in different modes.
摘要翻译：一种用于马桶的冲洗装置，包括在水箱内的支撑臂，该支撑臂包括与溢流管串联连接的检查构件，限制构件和出口阀，以及致动组件，其包括通过支撑臂与出口阀连接的致动器臂通过电梯线或链条。检查构件有助于改变冲洗水的排放量并以不同的模式顺利运行。

42. 发明授权

US08927374B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08927374B2
公开(公告)日：2015-01-06
申请号：US13252346
申请日：2011-10-04
申请人： Lilly Su , Pang-Yen Tsai , Tze-Liang Lee , Chii-Horng Li , Yen-Ru Lee , Ming-Hua Yu
发明人： Lilly Su , Pang-Yen Tsai , Tze-Liang Lee , Chii-Horng Li , Yen-Ru Lee , Ming-Hua Yu
IPC分类号： H01L21/336 , H01L29/04 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/08
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/0617 , H01L29/045 , H01L29/0653 , H01L29/0843 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.
摘要翻译：公开了一种制造半导体器件的方法。应变材料形成在衬底的空腔中并与衬底中的隔离结构相邻。应变材料在基底表面上方有一角。所公开的方法提供了一种用于在隔离结构附近形成应变材料的改进方法，其中在衬底的空腔中增加部分以增强载体移动性并提高器件性能。改进的形成方法通过提供一种处理来重新分布空腔中角部的至少一部分来实现。

43. 发明授权

US08835267B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08835267B2
公开(公告)日：2014-09-16
申请号：US13248319
申请日：2011-09-29
申请人： Yen-Ru Lee , Ming-Hua Yu , Tze-Liang Lee , Chii-Horng Li , Pang-Yen Tsai , Lilly Su , Yi-Hung Lin , Yu-Hung Cheng
发明人： Yen-Ru Lee , Ming-Hua Yu , Tze-Liang Lee , Chii-Horng Li , Pang-Yen Tsai , Lilly Su , Yi-Hung Lin , Yu-Hung Cheng
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7846
摘要： A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity.
摘要翻译：公开了一种制造半导体器件的方法。应变材料形成在衬底的空腔中并与衬底中的隔离结构相邻。应变材料在基底表面上方有一角。所公开的方法提供了一种用于形成邻近隔离结构的应变材料的改进方法，其中衬底的腔中具有增加的部分，以增强载体移动性并提高器件性能。在一个实施例中，改进的形成方法是通过使用蚀刻工艺来实现的，该蚀刻工艺通过去除位于空腔中的角部的至少一部分来重新分布应变材料。

44. 发明申请

US20130082309A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130082309A1
公开(公告)日：2013-04-04
申请号：US13252346
申请日：2011-10-04
申请人： Lilly SU , Pang-Yen TSAI , Tze-Liang LEE , Chii-Horng LI , Yen-Ru LEE , Ming-Hua YU
发明人： Lilly SU , Pang-Yen TSAI , Tze-Liang LEE , Chii-Horng LI , Yen-Ru LEE , Ming-Hua YU
IPC分类号： H01L29/772 , H01L21/336 , H01L21/02
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/0617 , H01L29/045 , H01L29/0653 , H01L29/0843 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.
摘要翻译：公开了一种制造半导体器件的方法。应变材料形成在衬底的空腔中并与衬底中的隔离结构相邻。应变材料在基底表面上方有一角。所公开的方法提供了一种用于在隔离结构附近形成应变材料的改进方法，其中在衬底的空腔中增加部分以增强载体移动性并提高器件性能。改进的形成方法通过提供一种处理来重新分布空腔中角部的至少一部分来实现。

45. 发明授权

US08255843B2 Method of manufacturing strained-silicon semiconductor device 有权
标题翻译：制造应变硅半导体器件的方法
公开(公告)号：US08255843B2
公开(公告)日：2012-08-28
申请号：US12870365
申请日：2010-08-27
申请人： Yun-Hsiu Chen , Syun-Ming Jang , Pang-Yen Tsai
发明人： Yun-Hsiu Chen , Syun-Ming Jang , Pang-Yen Tsai
IPC分类号： G06F17/50
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/7848
摘要： A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in selectively grown epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a possibility of such defects occurring exists, a dummy pattern of epitaxial structures may be indicated. If so, the dummy pattern appropriate to the proposed layout is created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.
摘要翻译：一种用于制造应变硅半导体器件以改善选择性生长的外延膜厚度的不期望的变化的方法。评估所提出的半导体器件的布局或组件配置以确定相对较轻或密集的群体的区域，以便确定是否可能发生局部加载效应的缺陷。如果存在这种缺陷的可能性，则可以指示外延结构的虚拟图案。如果是这样，则创建适合于所提出的布局的虚拟图案，并入到掩模设计中，然后与原始提出的部件配置一起在基板上实现。

46. 发明申请

US20120012047A1 METHOD OF TEMPERATURE DETERMINATION FOR DEPOSITION REACTORS 有权
标题翻译：沉积反应器温度测定方法
公开(公告)号：US20120012047A1
公开(公告)日：2012-01-19
申请号：US12835789
申请日：2010-07-14
申请人： Jhi-Cherng LU , Jr-Hung LI , Chii-Horng LI , Pang-Yen TSAI , Bing-Hung CHEN , Tze-Liang LEE
发明人： Jhi-Cherng LU , Jr-Hung LI , Chii-Horng LI , Pang-Yen TSAI , Bing-Hung CHEN , Tze-Liang LEE
IPC分类号： C30B25/10
CPC分类号： C30B25/16 , C30B29/06 , C30B29/08 , C30B29/52 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L22/10 , H01L22/12 , Y10T117/1004 , Y10T117/1008
摘要： A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.
摘要翻译：确定沉积反应器中的温度的方法包括以下步骤：将硅锗的第一外延层沉积在衬底上，在第一外延层上沉积硅的第二外延层，测量第二外延层的厚度并确定使用测量的第二外延层的厚度在沉积反应器中的温度。该方法还可以包括使用加热装置和温度测量装置将沉积反应器加热至约预定温度，并产生指示沉积反应器内的温度的信号。该方法还可以包括以下步骤：将测量的厚度与对应于预定温度的第二外延层的预定厚度进行比较，并使用第二外延层的测量厚度和第二外延层的预定厚度来确定沉积反应器中的温度外延层。

47. 发明授权

US07816217B2 Multi-step epitaxial process for depositing Si/SiGe 有权
标题翻译：用于沉积Si / SiGe的多步外延工艺
公开(公告)号：US07816217B2
公开(公告)日：2010-10-19
申请号：US11313768
申请日：2005-12-22
申请人： Li-Te S. Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
发明人： Li-Te S. Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02661
摘要： A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.
摘要翻译：一种制造半导体器件的方法包括提供包括硅的衬底，清洁衬底，使用第一源气体执行第一低压化学气相沉积（LPCVD）工艺，以在衬底上选择性地沉积硅（Si）晶种层，使用第二源气体执行第二LPCVD处理，以选择性地在所述Si层上沉积第一层硅锗（SiGe），所述第二源气体以第一流速包括盐酸盐，并且使用第三源进行第三LPCVD处理气体包括盐酸盐以第二流量。第一流速基本上低于第二流量。

48. 发明授权

US07538387B2 Stack SiGe for short channel improvement 有权
标题翻译： Stack SiGe用于短信道改进
公开(公告)号：US07538387B2
公开(公告)日：2009-05-26
申请号：US11653687
申请日：2007-01-16
申请人： Pang-Yen Tsai
发明人： Pang-Yen Tsai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , Y10S257/90
摘要： A semiconductor structure includes a first compound layer including an element, and a first impurity having a first impurity concentration; and a second compound layer including the element and a second impurity of a same conductivity type as the first impurity, wherein the second impurity has a second impurity concentration, and wherein the second compound layer is on the first compound layer. The semiconductor structure further includes a third compound layer including the element and a third impurity of a same conductivity type as the first impurity, wherein the third impurity has a third impurity concentration, and wherein the third compound layer is on the second compound layer, and wherein the second impurity concentration is substantially lower than the first and the third impurity concentrations.
摘要翻译：半导体结构包括含有元素的第一化合物层和具有第一杂质浓度的第一杂质; 以及第二化合物层，其包含所述元素和与所述第一杂质相同的导电类型的第二杂质，其中所述第二杂质具有第二杂质浓度，并且其中所述第二化合物层在所述第一化合物层上。半导体结构还包括第三化合物层，该第三化合物层包括与第一杂质相同导电类型的元素和第三杂质，其中第三杂质具有第三杂质浓度，并且其中第三化合物层位于第二化合物层上，以及其中所述第二杂质浓度基本上低于所述第一和第三杂质浓度。

49. 发明授权

US07504292B2 Short channel effect engineering in MOS device using epitaxially carbon-doped silicon 有权
标题翻译：使用外延碳掺杂硅的MOS器件中的短沟道效应工程
公开(公告)号：US07504292B2
公开(公告)日：2009-03-17
申请号：US11633721
申请日：2006-12-05
申请人： Keh-Chiang Ku , Pang-Yen Tsai , Chun-Feng Nieh , Li-Ting Wang
发明人： Keh-Chiang Ku , Pang-Yen Tsai , Chun-Feng Nieh , Li-Ting Wang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.
摘要翻译：一种用于形成半导体结构的方法包括提供半导体衬底，在半导体衬底上形成栅极堆叠，以及外围生长与栅堆叠相邻的轻掺杂源极/漏极（LDD）区域，其中碳同时掺杂到LDD区域。

50. 发明授权

US07465972B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US07465972B2
公开(公告)日：2008-12-16
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L31/62
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

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