专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20100254191A1 SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY 有权
标题翻译：包含三维存储器单元阵列的半导体存储器件
公开(公告)号：US20100254191A1
公开(公告)日：2010-10-07
申请号：US12752485
申请日：2010-04-01
申请人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： G11C16/02 , H01L21/3205
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 以及多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上方延伸的第二部分，其中多个字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

32. 发明授权

US09147492B2 Control method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的控制方法
公开(公告)号：US09147492B2
公开(公告)日：2015-09-29
申请号：US14546477
申请日：2014-11-18
申请人： Sunil Shim , Jin-Man Han , Sang-Wan Nam , Won-Taeck Jung
发明人： Sunil Shim , Jin-Man Han , Sang-Wan Nam , Won-Taeck Jung
IPC分类号： G11C16/00 , G11C16/34 , G11C16/10 , G11C16/16 , H01L27/115 , H01L29/792 , G11C16/14
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/349 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block.
摘要翻译：根据示例性实施例，一种非易失性存储器件的控制方法，其包括在衬底上的多个存储块，每个存储块包括沿垂直于衬底的方向堆叠的多个子块，并且被配置为独立擦除，每个子块包括在垂直于衬底的方向上堆叠的多个存储单元。控制方法包括将第一存储块的计数值与参考值进行比较，所述计数值根据在第一存储器块中的数据被编程之后在第一存储器块执行的程序，读取或擦除操作的数量确定; 并且如果所述计数值大于或等于所述参考值，则执行重新编程操作，其中在第一存储器块中编程的数据被读取并且所读取的数据被编程在第二存储器块中。

33. 发明授权

US08873294B2 Nonvolatile memory devices, erasing methods thereof and memory systems including the same 有权
标题翻译：非易失性存储器件，其擦除方法和包括其的存储器系统
公开(公告)号：US08873294B2
公开(公告)日：2014-10-28
申请号：US13295335
申请日：2011-11-14
申请人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
发明人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
IPC分类号： G11C16/16 , G11C16/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , H01L29/792 , G11C16/30 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.
摘要翻译：提供了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。所述擦除方法包括将地电压施加到与所述电池串的地选择晶体管连接的接地选择线; 将接地电压施加到与电池串的选择晶体管连接的串选择线; 对与单元串的存储单元连接的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

34. 发明授权

US08823072B2 Floating gate type nonvolatile memory device and related methods of manufacture and operation 有权
标题翻译：浮门式非易失性存储器件及相关制造和操作方法
公开(公告)号：US08823072B2
公开(公告)日：2014-09-02
申请号：US13074219
申请日：2011-03-29
申请人： Jae Ho Kim , Sung-Hwan Jang , Hye-Young Kwon , Sunil Shim , Hyun-Sil Oh
发明人： Jae Ho Kim , Sung-Hwan Jang , Hye-Young Kwon , Sunil Shim , Hyun-Sil Oh
IPC分类号： H01L29/788 , H01L27/115 , H01L29/423
CPC分类号： H01L29/7889 , H01L27/11551 , H01L27/11556 , H01L29/42324
摘要： A floating gate type nonvolatile memory device comprises a semiconductor layer, wordlines crossing over the semiconductor layer, and a memory element disposed between the wordlines and facing the semiconductor layer.
摘要翻译：浮栅型非易失性存储器件包括半导体层，跨越半导体层的字线和设置在字线之间并且面向半导体层的存储元件。

35. 发明授权

US08576629B2 Operating method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US08576629B2
公开(公告)日：2013-11-05
申请号：US13315523
申请日：2011-12-09
申请人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线多个第一选择线。

36. 发明申请

US20130182502A1 Operating Methods of Nonvolatile Memory Devices 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US20130182502A1
公开(公告)日：2013-07-18
申请号：US13784969
申请日：2013-03-05
申请人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
发明人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
IPC分类号： G11C16/14 , G11C7/14
CPC分类号： G11C16/14 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings; floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。所述方法可以包括将字线擦除电压施加到连接到所述多个单元串的存储单元的字线; 连接到多个单元串的接地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

37. 发明授权

US08488402B2 Nonvolatile memory device and method of reading the same using different precharge voltages 有权
标题翻译：非易失性存储器件以及使用不同的预充电电压来读取它们的方法
公开(公告)号：US08488402B2
公开(公告)日：2013-07-16
申请号：US13280421
申请日：2011-10-25
申请人： Sunil Shim , Woonkyung Lee , Jaehoon Jang , Kihyun Kim
发明人： Sunil Shim , Woonkyung Lee , Jaehoon Jang , Kihyun Kim
IPC分类号： G11C11/34 , G11C16/04 , G11C7/10
CPC分类号： G11C7/12 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C2216/14 , H01L27/0688 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, multiple doping regions, multiple cell strings and multiple page buffers. The doping regions extend in a first direction along the substrate and are spaced apart from one another in a second direction. The cell strings are provided according to a specific pattern between adjacent first and second doping regions among the multiple regions, each of the cell strings including multiple cell transistors stacked in a third direction perpendicular to the substrate. The page buffers are connected to the cell strings through bit lines, the page buffers being configured to provide precharge voltages to the bit lines during a read operation. Levels of the precharge voltages provided to the bit lines vary depending on distances between the cell strings and at least one of the first and second doping regions, respectively.
摘要翻译：非易失性存储器件包括衬底，多个掺杂区域，多个单元串和多页缓冲器。掺杂区域沿着衬底在第一方向上延伸并且在第二方向上彼此间隔开。根据多个区域中的相邻的第一和第二掺杂区域之间的特定图案提供单元串，每个单元串包括在与基板垂直的第三方向上堆叠的多个单元晶体管。页缓冲器通过位线连接到单元串，页缓冲器被配置为在读操作期间向位线提供预充电电压。提供给位线的预充电电压的电平分别根据电池串与第一和第二掺杂区域中的至少一个之间的距离而变化。

38. 发明申请

US20100193861A1 Three-Dimensional Memory Device 有权
标题翻译：三维存储器件
公开(公告)号：US20100193861A1
公开(公告)日：2010-08-05
申请号：US12694339
申请日：2010-01-27
申请人： Sunil Shim , Hansoo Kim , Jaehoon Jang , Jaehun Jeong
发明人： Sunil Shim , Hansoo Kim , Jaehoon Jang , Jaehun Jeong
IPC分类号： H01L29/78
CPC分类号： H01L27/11551 , G11C16/0483 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer.
摘要翻译：三维半导体器件包括：半导体衬底，以矩阵形式布置在半导体衬底上的垂直沟道结构;设置在半导体衬底处以与垂直沟道结构直接相连的P型半导体层;以及布置的公共源极线在垂直沟道结构之间的半导体衬底处。公共源极线可以与P型半导体层接触。

39. 发明申请

US20100109065A1 THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES HAVING SUB-DIVIDED ACTIVE BARS AND METHODS OF MANUFACTURING SUCH DEVICES 有权
标题翻译：具有分包活性棒的三维非易失性存储器件及其制造方法
公开(公告)号：US20100109065A1
公开(公告)日：2010-05-06
申请号：US12612125
申请日：2009-11-04
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

40. 发明授权

US09679659B2 Methods of operating a nonvolatile memory device 有权
公开(公告)号：US09679659B2
公开(公告)日：2017-06-13
申请号：US14859637
申请日：2015-09-21
申请人： Sunil Shim , Joon-sung Lim , Jin-Kyu Kang , Euido Kim , Jang-Gn Yun
发明人： Sunil Shim , Joon-sung Lim , Jin-Kyu Kang , Euido Kim , Jang-Gn Yun
IPC分类号： G11C16/04 , G11C16/16 , G11C16/34 , G11C11/56
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/3445
摘要： An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式