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1. 发明授权

US10199116B2 Non-volatile memory devices, operating methods thereof and memory systems including the same 有权
公开(公告)号：US10199116B2
公开(公告)日：2019-02-05
申请号：US15664303
申请日：2017-07-31
申请人： Sun-Il Shim , Jae-Hoon Jang , Donghyuk Chae , Youngho Lim , Hansoo Kim , Jaehun Jeong
发明人： Sun-Il Shim , Jae-Hoon Jang , Donghyuk Chae , Youngho Lim , Hansoo Kim , Jaehun Jeong
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04 , H01L27/11582 , G11C16/08 , G11C16/12 , G11C16/14 , G11C16/26 , H01L27/1157
摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

2. 发明申请

US20150348637A1 NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开
公开(公告)号：US20150348637A1
公开(公告)日：2015-12-03
申请号：US14820895
申请日：2015-08-07
申请人： Jinman HAN , Sun-Il SHIM , Donghyuk CHAE , Jae-Hoon JANG , Youngho LIM , Hansoo KIM , Jaehun JEONG
发明人： Jinman HAN , Sun-Il SHIM , Donghyuk CHAE , Jae-Hoon JANG , Youngho LIM , Hansoo KIM , Jaehun JEONG
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/3418 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

3. 发明授权

US08896123B2 Nonvolatile memory devices having a three dimensional structure 有权
标题翻译：具有三维结构的非易失性存储器件
公开(公告)号：US08896123B2
公开(公告)日：2014-11-25
申请号：US13478482
申请日：2012-05-23
申请人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
发明人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
IPC分类号： H01L27/115 , H01L23/522 , H01L29/792 , H01L29/94
CPC分类号： H01L27/11578 , H01L27/115 , H01L27/11517 , H01L27/11565 , H01L27/11582
摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
摘要翻译：具有三维结构的非易失性存储装置。非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

4. 发明申请

US20100193861A1 Three-Dimensional Memory Device 有权
标题翻译：三维存储器件
公开(公告)号：US20100193861A1
公开(公告)日：2010-08-05
申请号：US12694339
申请日：2010-01-27
申请人： Sunil Shim , Hansoo Kim , Jaehoon Jang , Jaehun Jeong
发明人： Sunil Shim , Hansoo Kim , Jaehoon Jang , Jaehun Jeong
IPC分类号： H01L29/78
CPC分类号： H01L27/11551 , G11C16/0483 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer.
摘要翻译：三维半导体器件包括：半导体衬底，以矩阵形式布置在半导体衬底上的垂直沟道结构;设置在半导体衬底处以与垂直沟道结构直接相连的P型半导体层;以及布置的公共源极线在垂直沟道结构之间的半导体衬底处。公共源极线可以与P型半导体层接触。

5. 发明授权

US09378831B2 Nonvolatile memory devices, operating methods thereof and memory systems including the same 有权
标题翻译：非易失性存储器件，其操作方法和包括其的存储器系统
公开(公告)号：US09378831B2
公开(公告)日：2016-06-28
申请号：US14820895
申请日：2015-08-07
申请人： Jinman Han , Sun-Il Shim , Donghyuk Chae , Jae-Hoon Jang , Youngho Lim , Hansoo Kim , Jaehun Jeong
发明人： Jinman Han , Sun-Il Shim , Donghyuk Chae , Jae-Hoon Jang , Youngho Lim , Hansoo Kim , Jaehun Jeong
IPC分类号： G11C16/04 , G11C16/14 , G11C16/16 , G11C16/08 , G11C16/12 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/3418 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.
摘要翻译：非易失性存储器件，其操作方法和包括该非易失性存储器件的存储器系统。在操作方法中，连接到位线的第一串的接地选择线可以浮置。可以将擦除禁止电压施加到连接到位线的第二串的接地选择线。可以将擦除操作电压施加到第一和第二串。

6. 发明授权

US09012977B2 Semiconductor memory devices having selection transistors with nonuniform threshold voltage characteristics 有权
标题翻译：具有选择晶体管的半导体存储器件具有不均匀的阈值电压特性
公开(公告)号：US09012977B2
公开(公告)日：2015-04-21
申请号：US14154834
申请日：2014-01-14
申请人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Su-Youn Yi , Jaehoon Jang , Sunghoi Hur
发明人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Su-Youn Yi , Jaehoon Jang , Sunghoi Hur
IPC分类号： H01L29/792 , H01L29/66 , H01L27/02 , H01L27/115
CPC分类号： H01L27/0207 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.
摘要翻译：提供了一种半导体存储器件。在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

7. 发明申请

US20130075807A1 SEMICONDUCTOR MEMORY DEVICES HAVING SELECTION TRANSISTORS WITH NONUNIFORM THRESHOLD VOLTAGE CHARACTERISTICS 有权
标题翻译：具有非线性阈值电压特性的选择晶体管的半导体存储器件
公开(公告)号：US20130075807A1
公开(公告)日：2013-03-28
申请号：US13684857
申请日：2012-11-26
申请人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Sunghoi Hur , Jaehoon Jang , Su-Youn Yi
发明人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Sunghoi Hur , Jaehoon Jang , Su-Youn Yi
IPC分类号： H01L29/792
CPC分类号： H01L27/0207 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.
摘要翻译：提供了一种半导体存储器件。在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

8. 发明授权

US08203211B2 Nonvolatile memory devices having a three dimensional structure 有权
标题翻译：具有三维结构的非易失性存储器件
公开(公告)号：US08203211B2
公开(公告)日：2012-06-19
申请号：US12798525
申请日：2010-04-06
申请人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
发明人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
IPC分类号： H01L27/115 , H01L23/522
CPC分类号： H01L27/11578 , H01L27/115 , H01L27/11517 , H01L27/11565 , H01L27/11582
摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
摘要翻译：具有三维结构的非易失性存储装置。非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

9. 发明授权

US08115259B2 Three-dimensional memory device 有权
标题翻译：三维存储设备
公开(公告)号：US08115259B2
公开(公告)日：2012-02-14
申请号：US12694339
申请日：2010-01-27
申请人： Sunil Shim , Hansoo Kim , Jaehoon Jang , Jaehun Jeong
发明人： Sunil Shim , Hansoo Kim , Jaehoon Jang , Jaehun Jeong
IPC分类号： H01L21/70
CPC分类号： H01L27/11551 , G11C16/0483 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer.
摘要翻译：三维半导体器件包括：半导体衬底，以矩阵形式布置在半导体衬底上的垂直沟道结构;设置在半导体衬底处以与垂直沟道结构直接相连的P型半导体层;以及布置的公共源极线在垂直沟道结构之间的半导体衬底处。公共源极线可以与P型半导体层接触。

10. 发明申请

US20100315875A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 有权
标题翻译：具有垂直结构的非易失性存储器件及其操作方法
公开(公告)号：US20100315875A1
公开(公告)日：2010-12-16
申请号：US12860049
申请日：2010-08-20
申请人： Doogon Kim , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jaehun Jeong
发明人： Doogon Kim , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jaehun Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.
摘要翻译：提供了一种操作非易失性存储器件的方法。该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到与第一和第二NAND串的存储单元相连的字线。

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