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1. 发明授权

US08873294B2 Nonvolatile memory devices, erasing methods thereof and memory systems including the same 有权
标题翻译：非易失性存储器件，其擦除方法和包括其的存储器系统
公开(公告)号：US08873294B2
公开(公告)日：2014-10-28
申请号：US13295335
申请日：2011-11-14
申请人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
发明人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
IPC分类号： G11C16/16 , G11C16/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , H01L29/792 , G11C16/30 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.
摘要翻译：提供了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。所述擦除方法包括将地电压施加到与所述电池串的地选择晶体管连接的接地选择线; 将接地电压施加到与电池串的选择晶体管连接的串选择线; 对与单元串的存储单元连接的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

2. 发明申请

US20120120740A1 Nonvolatile Memory Devices, Erasing Methods Thereof and Memory Systems Including the Same 有权
标题翻译：非易失性存储器件，其擦除方法和包括其的存储器系统
公开(公告)号：US20120120740A1
公开(公告)日：2012-05-17
申请号：US13295335
申请日：2011-11-14
申请人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
发明人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
IPC分类号： G11C7/00
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Disclosed are erase methods for a memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the plurality of cell strings; applying a ground voltage to string selection lines connected with selection transistors of the plurality of cell strings; applying a word line erase voltage to word lines connected with memory cells of the plurality of cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.
摘要翻译：公开了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。所述擦除方法包括将地电压施加到与所述多个单元串的接地选择晶体管相连的接地选择线; 对与所述多个单元串的选择晶体管连接的串选择线施加接地电压; 对与多个单元串的存储单元相连的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

3. 发明申请

US20130182502A1 Operating Methods of Nonvolatile Memory Devices 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US20130182502A1
公开(公告)日：2013-07-18
申请号：US13784969
申请日：2013-03-05
申请人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
发明人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
IPC分类号： G11C16/14 , G11C7/14
CPC分类号： G11C16/14 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings; floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。所述方法可以包括将字线擦除电压施加到连接到所述多个单元串的存储单元的字线; 连接到多个单元串的接地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

4. 发明授权

US08488402B2 Nonvolatile memory device and method of reading the same using different precharge voltages 有权
标题翻译：非易失性存储器件以及使用不同的预充电电压来读取它们的方法
公开(公告)号：US08488402B2
公开(公告)日：2013-07-16
申请号：US13280421
申请日：2011-10-25
申请人： Sunil Shim , Woonkyung Lee , Jaehoon Jang , Kihyun Kim
发明人： Sunil Shim , Woonkyung Lee , Jaehoon Jang , Kihyun Kim
IPC分类号： G11C11/34 , G11C16/04 , G11C7/10
CPC分类号： G11C7/12 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C2216/14 , H01L27/0688 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, multiple doping regions, multiple cell strings and multiple page buffers. The doping regions extend in a first direction along the substrate and are spaced apart from one another in a second direction. The cell strings are provided according to a specific pattern between adjacent first and second doping regions among the multiple regions, each of the cell strings including multiple cell transistors stacked in a third direction perpendicular to the substrate. The page buffers are connected to the cell strings through bit lines, the page buffers being configured to provide precharge voltages to the bit lines during a read operation. Levels of the precharge voltages provided to the bit lines vary depending on distances between the cell strings and at least one of the first and second doping regions, respectively.
摘要翻译：非易失性存储器件包括衬底，多个掺杂区域，多个单元串和多页缓冲器。掺杂区域沿着衬底在第一方向上延伸并且在第二方向上彼此间隔开。根据多个区域中的相邻的第一和第二掺杂区域之间的特定图案提供单元串，每个单元串包括在与基板垂直的第三方向上堆叠的多个单元晶体管。页缓冲器通过位线连接到单元串，页缓冲器被配置为在读操作期间向位线提供预充电电压。提供给位线的预充电电压的电平分别根据电池串与第一和第二掺杂区域中的至少一个之间的距离而变化。

5. 发明授权

US09136005B2 Erasing methods of three-dimensional nonvolatile memory devices with cell strings and dummy word lines 有权
标题翻译：具有单元串和虚拟字线的三维非易失性存储器件的擦除方法
公开(公告)号：US09136005B2
公开(公告)日：2015-09-15
申请号：US13784969
申请日：2013-03-05
申请人： Byeong-In Choe , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
发明人： Byeong-In Choe , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
IPC分类号： G11C16/14 , G11C7/14 , G11C16/30 , H01L29/792 , H01L27/115 , G11C16/10 , G11C16/04 , G11C16/16
CPC分类号： G11C16/14 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Methods of operating a nonvolatile memory device may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings, floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings, applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings, applying an erase voltage to the substrate, and floating the at least one lower dummy word line after applying of the erase voltage.
摘要翻译：操作非易失性存储器件的方法可以包括将字线擦除电压施加到连接到多个单元串中的存储单元的字线，连接到多个单元串的接地选择晶体管的浮动地选择线和连接到多个单元串中的串选择晶体管，对连接到多个单元串中的每个单元串中的至少一个下存储单元之间的下虚拟存储单元的至少一个下虚拟字线施加接地电压，擦除电压到衬底，并且在施加擦除电压之后浮置至少一个下部虚拟字线。

6. 发明申请

US20120099387A1 NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME USING DIFFERENT PRECHARGE VOLTAGES 有权
标题翻译：非易失性存储器件及其使用不同预置电压读取相同方法
公开(公告)号：US20120099387A1
公开(公告)日：2012-04-26
申请号：US13280421
申请日：2011-10-25
申请人： Sunil Shim , Woonkyung Lee , Jaehoon Jang , Kihyun Kim
发明人： Sunil Shim , Woonkyung Lee , Jaehoon Jang , Kihyun Kim
IPC分类号： G11C7/10 , G11C7/12
CPC分类号： G11C7/12 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C2216/14 , H01L27/0688 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, multiple doping regions, multiple cell strings and multiple page buffers. The doping regions extend in a first direction along the substrate and are spaced apart from one another in a second direction. The cell strings are provided according to a specific pattern between adjacent first and second doping regions among the multiple regions, each of the cell strings including multiple cell transistors stacked in a third direction perpendicular to the substrate. The page buffers are connected to the cell strings through bit lines, the page buffers being configured to provide precharge voltages to the bit lines during a read operation. Levels of the precharge voltages provided to the bit lines vary depending on distances between the cell strings and at least one of the first and second doping regions, respectively.
摘要翻译：非易失性存储器件包括衬底，多个掺杂区域，多个单元串和多页缓冲器。掺杂区域沿着衬底在第一方向上延伸并且在第二方向上彼此间隔开。根据多个区域中的相邻的第一和第二掺杂区域之间的特定图案提供单元串，每个单元串包括在与基板垂直的第三方向上堆叠的多个单元晶体管。页缓冲器通过位线连接到单元串，页缓冲器被配置为在读操作期间向位线提供预充电电压。提供给位线的预充电电压的电平分别根据电池串与第一和第二掺杂区域中的至少一个之间的距离而变化。

7. 发明授权

US09111617B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US09111617B2
公开(公告)日：2015-08-18
申请号：US13585963
申请日：2012-08-15
申请人： Sunil Shim , Jang-gn Yun , Jeonghyuk Choi , Kwang Soo Seol , Jaehoon Jang , Jungdal Choi
发明人： Sunil Shim , Jang-gn Yun , Jeonghyuk Choi , Kwang Soo Seol , Jaehoon Jang , Jungdal Choi
IPC分类号： H01L29/78 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0466 , G11C16/0483 , H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.
摘要翻译：提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

8. 发明申请

US20130092994A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130092994A1
公开(公告)日：2013-04-18
申请号：US13585963
申请日：2012-08-15
申请人： Sunil SHIM , Jang-gn Yun , Jeonghyuk Choi , Kwang Soo Seol , Jaehoon Jang , Jungdal Choi
发明人： Sunil SHIM , Jang-gn Yun , Jeonghyuk Choi , Kwang Soo Seol , Jaehoon Jang , Jungdal Choi
IPC分类号： H01L29/78
CPC分类号： G11C16/0466 , G11C16/0483 , H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

9. 发明授权

US08576629B2 Operating method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US08576629B2
公开(公告)日：2013-11-05
申请号：US13315523
申请日：2011-12-09
申请人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线多个第一选择线。

10. 发明申请

US20100109065A1 THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES HAVING SUB-DIVIDED ACTIVE BARS AND METHODS OF MANUFACTURING SUCH DEVICES 有权
标题翻译：具有分包活性棒的三维非易失性存储器件及其制造方法
公开(公告)号：US20100109065A1
公开(公告)日：2010-05-06
申请号：US12612125
申请日：2009-11-04
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

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