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31. 发明授权

US06778020B2 High-frequency power amplifier 有权
标题翻译：高频功率放大器
公开(公告)号：US06778020B2
公开(公告)日：2004-08-17
申请号：US10379557
申请日：2003-03-06
申请人： Akira Ohta , Shingo Matsuda , Akira Inoue , Seiki Goto
发明人： Akira Ohta , Shingo Matsuda , Akira Inoue , Seiki Goto
IPC分类号： H03F304
CPC分类号： H03F1/56 , H03F3/191
摘要： A resonance circuit of a transmission line and a capacitor is connected to the base circuit of a transistor. The transmission line is shorter than one-quarter wavelength to make the resonant frequency of the resonant circuit higher than the frequency of a second harmonic. As a result, the angle of the reflection coefficient of the second harmonic when an input matching circuit side is viewed from the input terminal of the transistor ranges from 170° to 270° on a polar chart, and phase difference between the fundamental wave of the base current and the second harmonic decreases.
摘要翻译：传输线和电容器的谐振电路连接到晶体管的基极。传输线短于四分之一波长，以使谐振电路的谐振频率高于二次谐波的频率。结果，从极性图的晶体管的输入端子观察输入匹配电路侧的二次谐波的反射系数的角度在极坐标图上为170°〜270°，并且基波的相位差基极电流和二次谐波减小。

32. 发明授权

US06388941B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06388941B2
公开(公告)日：2002-05-14
申请号：US09903509
申请日：2001-07-13
申请人： Hiroshi Otori , Hiroki Fujisawa , Minoru Ebihara , Seiji Narui , Masanori Isoda , Akira Ohta
发明人： Hiroshi Otori , Hiroki Fujisawa , Minoru Ebihara , Seiji Narui , Masanori Isoda , Akira Ohta
IPC分类号： G11C800
CPC分类号： G11C29/70 , G11C5/025 , G11C5/063
摘要： Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.
摘要翻译：每个具有用于根据阈值电压差存储信息的可电气可编程电保险丝和地址比较器的排气单元（UNITb）设置在第二区域中，并且每个具有激光熔丝和地址比较器的释放单元（UNITa）设置在第一个区域。两个区域沿着每个比较器的地址信号布线彼此相邻，并且地址信号布线线性布置。即使电保险丝和激光熔丝被共存用于释放地址存储，也可以基于在地址信号布线的方向上延伸的大小来调整由于它们的配置之间的差异造成的片外占用面积之间的差异，并且可以从布局的观点最大限度地抑制片上占用面积的增加。

33. 发明授权

US5780129A Multi-layer blow-molded article 失效
标题翻译：多层吹塑制品
公开(公告)号：US5780129A
公开(公告)日：1998-07-14
申请号：US669346
申请日：1996-06-28
申请人： Akira Ohta
发明人： Akira Ohta
IPC分类号： B60R19/02 , B29C45/00 , B29C49/00 , B29C49/04 , B29C49/22 , B29C49/48 , B29C51/10 , B29C65/66 , B29K105/06 , B29L9/00 , B29L31/30 , B32B27/08 , B32B7/02 , B32B7/04
CPC分类号： B29C49/4802 , B29C49/0073 , B29C49/22 , B29C65/665 , B29C66/545 , B29C66/723 , B29C2049/4805 , B29C2049/4807 , B29C2049/4812 , B29C45/00 , B29C49/04 , B29C51/10 , B29C66/8322 , B29L2009/001 , B29L2031/3044 , Y10T428/1328 , Y10T428/1352 , Y10T428/24942
摘要： There is provided a multi-layer blow-molded article wherein in a multi-layer marginal-wall region formed of a plurality of layers, a convexly crooked portion projecting generally convexly from inside to outside is so formed that the molding shrinkage factor of a resin for use in a more outer layer is larger than that of a resin for use in a more inner layer, and a concavely crooked portion denting generally concavely from outside to inside is so formed that the molding shrinkage factor of a resin for use in a more outer layer is smaller than that of a resin for use in a more inner layer; and all the layers of the molded article are fittingly secured to each other by means of a clamping force resulting from the difference in molding shrinkage factors of the resins constituting the layers and/or portions defined in a circumferential direction in the multi-layer marginal-wall region.
摘要翻译： PCT No.PCT / JP95 / 00015 Sec。 371日期：1996年6月28日 102（e）日期1996年6月28日PCT 1995年1月11日PCT PCT。公开号WO95 / 18712 PCT 日期1995年7月13日提供了一种多层吹塑制品，其中在由多层形成的多层边缘壁区域中，形成从内到外大致凸出的凸形弯曲部分，使得成型用于更外层的树脂的收缩率大于用于更多内层的树脂的收缩率，并且形成从外部到内部大致凹陷的凹形弯曲部分，使得树脂的成型收缩率用于更外层的树脂比用于更多内层的树脂小; 并且模制品的所有层通过由多层边缘层中的构成层和/或周向限定的树脂的成型收缩率的差异导致的夹紧力彼此适配地固定，墙区域。

34. 发明授权

US5682114A Variable delay circuit, ring oscillator, and flip-flop circuit 失效
标题翻译：可变延迟电路，环形振荡器和触发器电路
公开(公告)号：US5682114A
公开(公告)日：1997-10-28
申请号：US545320
申请日：1995-10-19
申请人： Akira Ohta
发明人： Akira Ohta
IPC分类号： H03K3/03 , H03K3/037 , H03K5/00 , H03K5/13 , H03K7/08 , H03K17/28
CPC分类号： H03K3/0315 , H03K5/133 , H03K2005/00156
摘要： In a variable delay circuit for delaying an input signal by a variable delay time from a rising edge or a falling edge of the input signal to a rising edge or a falling edge of an output signal in a digital circuit, a data signal input terminal; a first signal input terminal to which a low-level signal of a logic gate is applied; n selector circuits (n=integer larger than 0) selecting either the signal at the data signal input terminal or the signal at the first signal input terminal in response to signals applied to first selector signal input terminals; and an (n+1)-input NOR circuit to which the signal at the data signal input terminal and output signals from the selector circuits are applied. In this variable delay circuit, a delay time shorter than the delay time of a single-stage buffer circuit can be controlled using only digital circuits.
摘要翻译：在用于将输入信号从输入信号的上升沿或下降沿延迟到数字电路中的输出信号的上升沿或下降沿的可变延迟电路的可变延迟电路中，数据信号输入端子; 施加逻辑门的低电平信号的第一信号输入端; 响应于施加到第一选择器信号输入端的信号，n个选择器电路（n =大于0的整数）选择数据信号输入端的信号或第一信号输入端的信号; 和数据信号输入端的信号和来自选择电路的输出信号的（n + 1）输入NOR电路。在该可变延迟电路中，可以仅使用数字电路来控制比单级缓冲电路的延迟时间短的延迟时间。

35. 发明授权

US5668491A Variable delay circuit 失效
标题翻译：可变延迟电路
公开(公告)号：US5668491A
公开(公告)日：1997-09-16
申请号：US585436
申请日：1996-01-11
申请人： Norio Higashisaka , Akira Ohta
发明人： Norio Higashisaka , Akira Ohta
IPC分类号： H03K5/13
CPC分类号： H03K5/133
摘要： A variable delay circuit includes a gate chain of first to n-th delay gates (n is an integer larger than 2) connected in series to each other via delay gate wirings having respective wiring lengths, the first delay gate receiving an input signal for delay; first to n-th separator gates to which the outputs of the first to n-th delay gates are input, respectively; first to n-th separator gate wirings having wiring lengths successively shortened from the first to n-th separator gate, first ends respectively connected to the first to n-th separator gates, and second ends connected to an n:1 selector, for selecting one of the outputs of the first to n-th separator gates in according with a select signal, and a select signal generating circuit for controlling the n:1 selector. The variable delay circuit has no loss of resolution due to parasitic capacitance of the delay gate wirings.
摘要翻译：可变延迟电路包括经由具有各自布线长度的延迟栅极布线彼此串联连接的第一至第n延迟门（n为大于2的整数）的栅极链，第一延迟栅极接收用于延迟的输入信号 ; 分别输入第一至第n延迟门的输出的第一至第n分离器门; 具有从第一至第n分离器栅极连续缩短的布线长度的第一至第n分离器栅极布线，分别连接到第一至第n分离器栅极的第一端和连接到n：1选择器的第二端，用于选择根据选择信号的第一至第n分离器门的输出中的一个，以及用于控制n：1选择器的选择信号发生电路。可变延迟电路由于延迟栅极布线的寄生电容而没有分辨率损失。

36. 发明授权

US5667748A Process and apparatus for multilayer blow molding and articles blow-molded therewith 失效
标题翻译：用于多层吹塑的方法和设备以及吹塑成型的制品
公开(公告)号：US5667748A
公开(公告)日：1997-09-16
申请号：US440686
申请日：1995-05-15
申请人： Akira Ohta , Kohsei Kushima , Satoshi Furuki
发明人： Akira Ohta , Kohsei Kushima , Satoshi Furuki
IPC分类号： B29C47/04 , B29C47/06 , B29C47/22 , B29C47/70 , B29C49/00 , B29C49/04 , B29C49/22
CPC分类号： B29C47/062 , B29C47/0023 , B29C47/065 , B29C47/22 , B29C47/265 , B29C47/268 , B29C47/705 , B29C49/0073 , B29C49/22 , B29C49/04 , B29L2031/3044 , B29L2031/771
摘要： This invention provides a blow molding process for manufacturing multilayer hollow articles having sections different from one another in respect to the kind of resins, number of layers, and thickness of layers along the circumference in the horizontal section of an article with the narrowest of the sections in any one of the resin layers extending in a specified width along the longitudinal wall of an article and being capable of satisfying the sectional performance requirements, an apparatus, and said hollow articles. It also provides a process for manufacturing multilayer hollow articles with the wall thickness ratio of resin layers in each section varying along the longitudinal wall of an article or those with the sectional width in each resin layer varying along the longitudinal wall of an article, an apparatus, and said hollow articles. Hollow articles molded by the process and apparatus of this invention are particularly useful for automotive bumpers, the seats and backs of chairs, and boiler-room doors.
摘要翻译：本发明提供一种吹塑成型方法，用于制造具有彼此不同的部分的多层中空制品，所述多个中空制品相对于具有最窄部分的制品的水平部分中的树脂种类，层数和层的厚度，在任何一个树脂层中，沿着制品的纵壁以特定的宽度延伸并且能够满足截面性能要求的装置和所述中空制品。它还提供了一种用于制造多层中空制品的方法，其中每个部分中的树脂层的壁厚比沿着制品的纵向壁变化，或者每个树脂层中的截面宽度沿着制品的纵向壁变化，，和所述中空制品。通过本发明的方法和装置模制的空心物品对于汽车保险杠，座椅和椅子背部以及锅炉室门特别有用。

37. 发明授权

US5661206A Fluidity control of cementitious compositions 失效
标题翻译：水泥组合物的流动性控制
公开(公告)号：US5661206A
公开(公告)日：1997-08-26
申请号：US579041
申请日：1995-12-21
申请人： Yoshio Tanaka , Akira Ohta , Hideyuki Tahara , Tsuyoshi Hirata
发明人： Yoshio Tanaka , Akira Ohta , Hideyuki Tahara , Tsuyoshi Hirata
IPC分类号： B01F17/52 , C04B24/26 , C04B24/32 , C04B40/00 , C08F2/04 , C08J3/215 , C08K5/06 , C08L33/00
CPC分类号： C04B24/2694 , C04B24/2647 , C04B24/267 , C04B24/32 , C04B40/0039 , C04B2103/30 , C04B2103/50
摘要： An admixture for modifying the fluidity of a cementitious mixture comprises a cement-dispersing agent which is an aqueous solution of polymer, in which solution an oxyalkylene-based defoaming agent is dissolved or dispersed in particles of no greater that 20 .mu.M diameter. The polymer is preferably a polymer which comprises units derived from unsaturated carboxylic acid monomer and the polymer is preferably prepared in the presence of the defoaming agent. Particular addition copolymers give particularly good results. The admixture permits good control of the fluidity of cementitious compositions and has extended shelf life.
摘要翻译：用于改变水泥混合物的流动性的混合物包括水泥分散剂，其是聚合物的水溶液，其中将氧化烯基消泡剂溶解或分散在不大于20μm直径的颗粒中。聚合物优选为包含衍生自不饱和羧酸单体的单元的聚合物，并且聚合物优选在消泡剂存在下制备。特别的加成共聚物具有特别好的结果。外加剂可以很好地控制水泥组合物的流动性，延长了保质期。

38. 发明授权

US5384214A Manufacturing of zinc-alkaline batteries 失效
标题翻译：制造锌碱电池
公开(公告)号：US5384214A
公开(公告)日：1995-01-24
申请号：US225938
申请日：1994-04-11
申请人： Sachiko Sugihara , Akira Miura , Akira Ohta
发明人： Sachiko Sugihara , Akira Miura , Akira Ohta
IPC分类号： H01M4/12 , C01F17/00 , C22C18/00 , H01M4/06 , H01M4/26 , H01M4/42 , H01M4/62 , H01M6/04 , H01M6/06 , H01M4/02
CPC分类号： H01M6/045 , C01F17/0043 , C22C18/00 , H01M4/42 , H01M4/62 , H01M6/06 , C01P2004/61 , C01P2004/62 , Y02P70/54
摘要： A non-pollution zinc-alkaline battery excellent in storage stability can be obtained by using, in formulation for negative electrode, a zinc alloy which contains at least one element selected from the group consisting of bismuth, lithium, calcium and aluminum which is free from mercury, lead, cadmium, indium and thallium is used as an active material and yttrium hydroxide or yttrium oxide optimized in a starting material therefor, particle size and weight loss on heat decomposition as an inorganic inhibitor. The storage stability of the battery can be further improved by adding to the above formulation for a negative electrode a proper amount of a surfactant having a polyethylene oxide group in hydrophilic group and a perfluoroalkyl group in oleophilic group as an organic inhibitor.
摘要翻译：通过在负极配方中使用含有选自铋，锂，钙和铝中的至少一种元素的锌合金，可以获得储存稳定性优异的无污染锌碱性电池，其不含使用汞，铅，镉，铟和铊作为活性物质，在其原料中优化氢氧化钇或氧化钇，在作为无机抑制剂的热分解时的粒度和重量损失。通过向上述配方中添加适量的亲水性基团中具有聚环氧乙烷的表面活性剂和亲油基团中的全氟烷基作为有机抑制剂，能够进一步提高电池的保存稳定性。

39. 发明授权

US5355027A Shift register circuit with three-input nor gates in selector circuit 失效
标题翻译：移位寄存器电路与选择电路中的三输入或门
公开(公告)号：US5355027A
公开(公告)日：1994-10-11
申请号：US42506
申请日：1993-04-05
申请人： Masaaki Shimada , Norio Higashisaka , Akira Ohta
发明人： Masaaki Shimada , Norio Higashisaka , Akira Ohta
IPC分类号： G11C19/38 , H03K3/286 , H03K19/20
CPC分类号： G11C19/38
摘要： A shift register circuit includes a first two-input NOR circuit to which a first data signal and a selection signal are input, a second two-input NOR circuit to which a first reverse data signal having an opposite phase from the first data signal and the selection signal are input, a third two-input NOR circuit to which a second data signal and a reverse selection signal having an opposite phase from the selection signal are input, a fourth two-input NOR circuit to which a second reverse data signal having an opposite phase from the second data signal and the reverse selection signal are input, a first three-input NOR circuit to which output signals from the first and third two-input NOR circuits and the clock signal are input, and a second three-input NOR circuit to which output signals from the second and fourth two-input NOR circuits and the clock signal are input. Since the three-input NOR circuits are employed, the number of NOR circuits through which the input data signal travels is decreased, resulting in an increase in the operation speed of the shift register circuit.
摘要翻译：移位寄存器电路包括输入第一数据信号和选择信号的第一双输入NOR电路;第二双输入NOR电路，具有与第一数据信号相反相位的第一反向数据信号和输入选择信号的第三双输入NOR电路，输入与选择信号具有相反相位的第二数据信号和反向选择信号的第三双输入NOR电路，具有第二反相数据信号的第二双输入NOR电路，输入与第二数据信号和反向选择信号相反的相位，输入来自第一和第三双输入NOR电路和时钟信号的输出信号的第一三输入NOR电路和第二三输入NOR电路输入来自第二和第四双输入NOR电路的输出信号和时钟信号的电路。由于采用三输入NOR电路，所以输入数据信号行进的NOR电路的数量减少，导致移位寄存器电路的操作速度增加。

40. 发明授权

US10240785B2 Driving method for solenoid valve, solenoid valve driving apparatus, and combustion apparatus including same 有权
公开(公告)号：US10240785B2
公开(公告)日：2019-03-26
申请号：US12929469
申请日：2011-01-27
申请人： Daisuke Konishi , Akira Ohta , Yoshihisa Kitano , Tomoya Nakano , Yoshifumi Atobe , Haruki Inoue , Yoshitaka Kimura , Ryo Ikeda , Tomoki Kishimoto , Yasuhide Ikeuchi , Tomoko Ikeuchi
发明人： Daisuke Konishi , Akira Ohta , Yoshihisa Kitano , Tomoya Nakano , Yoshifumi Atobe , Haruki Inoue , Yoshitaka Kimura , Ryo Ikeda , Tomoki Kishimoto , Yasuhide Ikeuchi
IPC分类号： F23N1/00 , F23N5/20 , F23K5/14 , H01H47/32
摘要： A solenoid valve driving apparatus includes switching means for ON/OFF-controlling application of a direct current voltage to a solenoid of a solenoid valve, and signal outputting means. A first period and a consecutive second period are set as a valve opening operation period of the solenoid valve. When the signal outputting means outputs the PWM signal to the switching means, a duty ratio of the output signal is set to be higher in the second period than in the first period so that a power supplied to the solenoid is larger in the second period than in the first period. As a result, a valve opening operation is performed in the solenoid valve reliably, and loud noise generation during the valve opening operation is suppressed.

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