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31. 发明专利

JPH05182474A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH05182474A
公开(公告)日：1993-07-23
申请号：JP5373292
申请日：1992-03-12
申请人： TOSHIBA CORP
发明人： ENDO TETSUO , SHIRATA RIICHIRO , OUCHI KAZUNORI , TANAKA YOSHIYUKI , KIRISAWA RYOHEI , ARITOME SEIICHI , TANAKA TOMOHARU , MOMOTOMI MASAKI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PURPOSE:To set the threshold value of a memory cell in an optimum state by confirming a writing lack state with first write verifying potential and confirming a writing excess state with second write verifying potential. CONSTITUTION:The writing lack state is checked by applying a first write verifying potential VVER(1) to a word line and applying a Vcc to a nonselective word line in a NAND cell and reading them after data is written in all memory cells connected to the selected word line. When writing lack is present, the memory cell is written and checked again. Thereafter, the writing excess state is checked by applying the second write verifying potential VVER(2) to the selective word line and applying the Vcc to the nonselective word line in the NAND cell and reading them. In such a manner, the threshold value of the memory cell is set in the optimum state and reliability is improved by controlling the write verifying checking the upper limit and the lower limit of an allowable threshold value.

32. 发明专利

JPH04278297A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04278297A
公开(公告)日：1992-10-02
申请号：JP4195191
申请日：1991-03-07
申请人： TOSHIBA CORP
发明人： KIRISAWA RYOHEI , ARITOME SEIICHI , NAKAYAMA RYOZO , ENDO TETSUO , INOUE CHIKA , SHIRATA RIICHIRO
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06
摘要： PURPOSE:To provide an EEPROM having a simple peripheral circuit and a high integration. CONSTITUTION:A bit line selecting transistor QBL is provided between an end of a bit line BL of an EEPROM memory cell array 21 having memory transistors and selecting gate transistors and a bit line driver 22, and a bit line undesired to be written is set to a floating state by controlling ON, OFF the transistor QBL at the time of writing data.

33. 发明专利

JPH03295097A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH03295097A
公开(公告)日：1991-12-26
申请号：JP9504990
申请日：1990-04-12
申请人： TOSHIBA CORP
发明人： ARITOME SEIICHI , SHIRATA RIICHIRO , MOMOTOMI MASAKI , IWATA YOSHIHISA , KIRISAWA RYOHEI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent destruction of insulation film of a selection gate transistor (TR) at repetitive erasure by applying a prescribed potential to a gate of the selection gate TR at the erasure in an EEPROM employing a memory TR having a floating gate and a control gate. CONSTITUTION:A NAND cell type EEPROM is formed with control gate TRs QS1, QS2) and memory TRs M1 - M4 each having a floating gate and a control gate provided on a substrate in series connection. Then in the case of erasure, control gates CG1 - CG4 of the TRs M1 - M4 are brought into 0V, and a high level such as 18V is applied to the substrate to apply 18V to also selection gate lines SG1 - SG2, then electrons of the floating gate of the TRs M1 - M4 are discharged to a P-channel well and a threshold level is moved in the negative direction to apply erasure. Even when the erasure is repeated in the method in which a similar high level to a level fed to the substrate is applied to the gate of the selection gate TR, the destruction of the insulation film of the control gate TR is prevented and the reliability of the EEPROM is enhanced.

34. 发明专利

JPH0316096A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0316096A
公开(公告)日：1991-01-24
申请号：JP15018689
申请日：1989-06-13
申请人： TOSHIBA CORP
发明人： NAKAYAMA RYOZO , SHIRATA RIICHIRO , ITO YASUO , KIRISAWA RYOHEI , OHIRA HIDEKO , MOMOTOMI MASAKI , IWATA YOSHIHISA , TANAKA TOMOHARU , ARITOME SEIICHI , ENDO TETSUO , MASUOKA FUJIO
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To effectively suppress the deterioration of reliability caused by the increase of a substrate current by providing a substrate potential fixing electrode on a prescribed part in a memory cell array area. CONSTITUTION:The nonvolatile semiconductor memory is provided with a memory cell array having memory cells M1 - M6 of a MOS transistor structure in which floating gates 41 - 48 and control gates 61 - 68 are laminated on a semiconductor substrate 1. Also, on a prescribed part of a field area of the memory cell array, a substrate potential fixing electrode 11 for coming into contact with the substrate 1 and fixing the substrate potential is provided. Accordingly, a substrate current generated at the time when a high potential of drains of the memory cells M1 - M6 is applied is absorbed, and a fluctuation of the substrate potential can be prevented. In such a way, the deterioration of an operation margin of an EPROM can be prevented.

35. 发明专利

JPH02177097A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH02177097A
公开(公告)日：1990-07-10
申请号：JP32973588
申请日：1988-12-27
申请人： TOSHIBA CORP
发明人： SHIRATA RIICHIRO , KIRISAWA RYOHEI , NAKAYAMA RYOZO , ARITOME SEIICHI , MOMOTOMI MASAKI , ITO YASUO , IWATA YOSHIHISA , ENDO TETSUO , TANAKA TOMOHARU , MASUOKA FUJIO
IPC分类号： G11C17/12 , G11C16/04 , G11C17/00
摘要： PURPOSE:To ensure the transmission of a bit line level to a selection memory cell and to reduce power consumption by utilizing electron discharge from a floating gate in the data erasure mode and electron injection to the floating gate in the data write mode. CONSTITUTION:An external program pulse VPPA is given to a bit line at data erasure, electrons of the floating gate are discharged from memory cells M1 - M8 closer to the bit line in the order to bring all memory cells to the state of data 1. At first, in the erasure of the memory cell M1, an H level is applied to a control line SD1 of a selected TR S1 at the bit line side, the voltage VPPA is applied to the bit line to apply an L level voltage to a control line SS1 and word lines WL2 - WL8. Thus, the M1 is brought into the erased state. The voltage VPPA is sent sequentially via the memory cell M2 and the memory cells M2 - M8 are erased. In the write mode, a program pulse VPPB from a boost circuit 14 is applied to the control gate of the selected cell to inject electrons to the floating gate to apply write while using a data as 0.

36. 发明专利

JPS63107058A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63107058A
公开(公告)日：1988-05-12
申请号：JP25066086
申请日：1986-10-23
申请人： TOSHIBA CORP
发明人： TAKENOUCHI NAOKO , ARITOME SEIICHI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To secure a sufficient element separation withstand voltage without enlarging an occupying area, and obtain a semiconductor device having a groove-type element separation or capacitor of high reliability, by a method wherein a burried layer is formed by an epitaxial growth technique, and then a groove is formed in the manner in which at least a bottom surface is brought into contact with the burried layer. CONSTITUTION:When a semiconductor device which has a groove-type element separation region or groove-type capacitor region on a semiconductor substrate is manufacture, an impurity burried layer 14 of the same conductivity type as the substrate 11 and an impurity burried layer 16 of inverse conductivity type are formed, by introducing impurity into the semiconductor substrate 11, and a semiconductor film 17 of the same conductivity type as the substrate 11 or of inverse type is formed by epitaxial growth. Then a groove 21 is formed in the element separation region or the capacitor region in the manner in which at least the bottom of the groove 21 is brought into contact with at least one part of the above mentioned burried layer 14. For example, an insulative film 23 for element separation is burried into the bottom of the above groove 21. On the sidewall of the groove 21 a capacitor electrode 26 is formed via a capacitor insulative film 25, and a DRAMFC cell is manufactured.

37. 发明专利

JP2002313970A SEMICONDUCTOR STORAGE 审中-公开
公开(公告)号：JP2002313970A
公开(公告)日：2002-10-25
申请号：JP2002048521
申请日：2002-02-25
申请人： TOSHIBA CORP
发明人： ENDO TETSUO , SHUDO SUSUMU , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide an NAND cell-type EEPROM that can reduce the element isolation region between NAND cells, and can improve integration. SOLUTION: The NAND cell is composed by connecting a plurality of memory cells in series. In the memory cell, a charge accumulation layer and a control gate are laminated on a semiconductor substrate while an insulating film is being sandwiched. In the EEPROM where the NAND cells are arranged in a matrix, a bit line 1 is arranged in the direction that orthogonally crosses a control gate CG used as a word line, the drain side of each NAND cell is connected to the bit line 1 by a bit line contact 2 via a selection transistor 5, and the adjacent bit line contacts 2 in each NAND cell are alternately shifted in the bit line direction.

38. 发明专利

JP2001148428A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001148428A
公开(公告)日：2001-05-29
申请号：JP32814999
申请日：1999-11-18
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： AIDA AKIRA , SHIRATA RIICHIRO , HAZAMA HIROAKI , SHIMIZU KAZUHIRO , IIZUKA HIROHISA , ARITOME SEIICHI , KOIDO NAOKI , MARUYAMA TORU , ARAI NORIHISA
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent the decline of the driving power of a transistor and the decline of reliability as much as possible. SOLUTION: This device is provided with the transistor provided with a gate insulation film 5 formed on the element area of a semiconductor substrate 2, a gate electrode formed on the gate insulation film and a diffusion layer 9 formed in the element area on both sides of the gate electrode, a side wall insulation film 11 formed at the side of the gate electrode of the transistor, a barrier insulation film 12 formed so as to cover the transistor and the side wall insulation film, and an intermediate film 11 formed between the diffusion layer and the barrier insulation film. The height of the boundary of the intermediate film and the barrier insulation film from the surface of the semiconductor substrate is made higher than the height of the boundary of the gate insulation film and the gate electrode from the surface of the semiconductor substrate.

39. 发明专利

JP2000114463A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000114463A
公开(公告)日：2000-04-21
申请号：JP27604598
申请日：1998-09-29
申请人： TOSHIBA CORP
发明人： TAKEUCHI YUJI , ARITOME SEIICHI , SHIRATA RIICHIRO , MURAHAMA YUICHIRO , ARAKI HITOSHI , UMEMURA MASASHI , YABANETA MASAMITSU , IKEDA OSAMU
IPC分类号： H01L27/04 , H01L21/762 , H01L21/768 , H01L21/822 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/78 , H01L29/94
摘要： PROBLEM TO BE SOLVED: To prevent a dielectric breakdown in a MOS structured insulation film thus improving reliability thereof. SOLUTION: An element region is shaped in a form of plurality of sides and corners, for instance, a square. A conductive film 16 to be one electrode of a MOS structure is arranged on the element region. The other electrode of the MOS structure is a silicon wafer. The conductive film 16 is arranged to cover at least the sides adjoining to each other and not to cover all the corners including contacting points (points of intersection) of the sides adjoining to each other. In the annular element region, the conductive film 16 is arranged not to cover all the corners including inside corners of the ring shaped element region.

40. 发明专利

JPH11163303A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH11163303A
公开(公告)日：1999-06-18
申请号：JP32594597
申请日：1997-11-27
申请人： TOSHIBA CORP
发明人： SHIMIZU KAZUHIRO , ARITOME SEIICHI
IPC分类号： G11C16/04 , H01L21/822 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To enable micronization and high integration of an element, improve isolation capability and reduce parasitic resistance, parasitic capacity, etc., a well by arranging an NAND string formed of a plurality of memory cell transistors with are connected in series mutually a matrix in a memory cell array. SOLUTION: A silicon thin film 12 is formed on an insulation layer 11 formed on a substrate 10. An insulation material is put between lattice-like silicon thin films 12 which function as element isolation. Each memory cell transistor is constituted of an n-type diffused layer 18, a floating gate electrode 15 formed on a channel region between the n-type diffused layers 18 via a gate oxide film 14 in between and a control gate electrode 17 formed on the floating gate electrode 15 via an insulation film 16 in between. Each selective gate transistor is constituted of n-type diffused layers 18, 18-S, 18-D and gate electrodes SGS, SGD formed on a channel between the n-type diffused layers 18, 18-S, 18-D with a gate oxide film 14A inbetween.

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