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1. 发明专利

JP2002170893A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002170893A
公开(公告)日：2002-06-14
申请号：JP2000364608
申请日：2000-11-30
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： AIDA AKIRA , SHIRATA RIICHIRO , HAZAMA HIROAKI , SHIMIZU KAZUHIRO , IIZUKA HIROHISA , ARITOME SEIICHI , KOIDO NAOKI , MARUYAMA TORU , ARAI NORIHISA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent dropping of driving power for a transistor as well as dropping of reliability, as possible. SOLUTION: There are provided a transistor which comprises a gate insulating film 5 formed on the element region of a semiconductor substrate 2, a gate electrode formed on the gate insulating film 5, a diffusion layer 9 formed on the element regions on both sides of the gate electrode, and a barrier insulating film 12 so formed as to cover the transistor and the diffusion layer 9. The height from the surface of semiconductor substrate 2 up to the barrier insulating film 12 is larger than that from the surface of semiconductor substrate up to the interface between the gate insulating film 5 and the gate electrode.

2. 发明专利

JP2001148428A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001148428A
公开(公告)日：2001-05-29
申请号：JP32814999
申请日：1999-11-18
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： AIDA AKIRA , SHIRATA RIICHIRO , HAZAMA HIROAKI , SHIMIZU KAZUHIRO , IIZUKA HIROHISA , ARITOME SEIICHI , KOIDO NAOKI , MARUYAMA TORU , ARAI NORIHISA
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent the decline of the driving power of a transistor and the decline of reliability as much as possible. SOLUTION: This device is provided with the transistor provided with a gate insulation film 5 formed on the element area of a semiconductor substrate 2, a gate electrode formed on the gate insulation film and a diffusion layer 9 formed in the element area on both sides of the gate electrode, a side wall insulation film 11 formed at the side of the gate electrode of the transistor, a barrier insulation film 12 formed so as to cover the transistor and the side wall insulation film, and an intermediate film 11 formed between the diffusion layer and the barrier insulation film. The height of the boundary of the intermediate film and the barrier insulation film from the surface of the semiconductor substrate is made higher than the height of the boundary of the gate insulation film and the gate electrode from the surface of the semiconductor substrate.

3. 发明专利

JP2010191984A Setting method of data storage system 有权
标题翻译：数据存储系统的设置方法
公开(公告)号：JP2010191984A
公开(公告)日：2010-09-02
申请号：JP2010093329
申请日：2010-04-14
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , AIDA AKIRA
IPC分类号： G06F12/16 , G11C29/04 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To provide a setting method of a data storage system capable of further reducing defective bit incidence rate seen from an external interface. SOLUTION: The setting method of data storage system includes: a non-spare area (1n) having a plurality of memory cell blocks and including pages connected to some of the memory cell blocks; a spare area (1s) having a plurality of spare memory cell blocks in which data is preliminarily aligned to a certain value and including pages connected to some of the spare memory cell blocks; and determination circuits (5, 6, 100) which detects at a data error of at least two bits when the data is read from the page in the non-spare area (1n), and determines the number of error bits in the read page by each read page. When a determination result by the determination circuit (100) is equal to or more than two bits, error correction of the content of the read page is performed, and the content of the read page is written in the page in the spare area (1s). COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够进一步减少从外部接口看到的有缺陷的比特率的数据存储系统的设置方法。解决方案：数据存储系统的设置方法包括：具有多个存储单元块的非备用区（1n），并且包括连接到一些存储单元块的页面; 具有多个备用存储单元块的备用区（1s），其中数据预先对齐到一定值，并且包括连接到一些备用存储单元块的页面; 以及当从非备用区（1n）中的页面读取数据时以至少两位的数据错误检测的确定电路（5,6,10），并确定读取页面中的错误位数通过每个阅读页面。当确定电路（100）的确定结果等于或大于两位时，执行读取页面的内容的错误校正，并且将读取的页面的内容写入备用区域中的页面（1s ）。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2008205493A Method for manufacturing nonvolatile semiconductor storage device 审中-公开
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：JP2008205493A
公开(公告)日：2008-09-04
申请号：JP2008098695
申请日：2008-04-04
申请人： Toshiba Corp , 株式会社東芝
发明人： AIDA AKIRA , NITTA HIROYUKI
IPC分类号： H01L21/8247 , H01L21/768 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To secure finely arranged lithographic margins of contacts and to eliminate mating disagreement with wiring. SOLUTION: A method of manufacturing a nonvolatile semiconductor storage device includes element regions and element isolation regions alternately arranged in stripe at a first pitch in a first direction, contact plugs made of conductive materials connected to the element regions and arranged at the first pitch in the first direction, and wirings connected to the contact plugs. The width of cross section of the contact plug sectioned at a plane perpendicular to the first direction has larger width at the contact bottom width defined as the width at the position connected to the element region than at the contact top width defined as the width at the position connected to the wiring and having larger width of the contact bottom width than the width of the element region. After embedding conductive materials between gates, when contact is formed, a wiring layer is formed with the conductive material of the contact by etching a linear pattern at the same time. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：确保精细布置的触点的平版印刷边缘，并消除与布线的配合不一致。解决方案：一种制造非易失性半导体存储装置的方法包括以第一方向以第一间距交替布置的元件区域和元件隔离区域，由导电材料制成的接触插塞连接到元件区域并且被布置在第一方向在第一方向上的间距，以及连接到接触插头的布线。在与第一方向垂直的平面处的接触塞截面的宽度在接触底部宽度处具有较大的宽度，该接触底部宽度被限定为连接到元件区域的位置处的宽度，而不是接触顶部宽度连接到布线并且具有比元件区域的宽度更大的接触底部宽度的宽度。在栅极之间埋入导电材料之后，当形成接触时，通过同时刻蚀线性图案，形成具有接触导电材料的布线层。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007018708A Data writing method for semiconductor memory device 有权
标题翻译：半导体存储器件的数据写入方法
公开(公告)号：JP2007018708A
公开(公告)日：2007-01-25
申请号：JP2006239310
申请日：2006-09-04
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , TAKEUCHI YUJI , AIDA AKIRA
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a data writing method for a semiconductor memory device in which erroneous read-out frequency can be reduced and data destruction possibility can be made small. SOLUTION: This data writing method for the semiconductor memory device has at least one second memory cell being adjacent to a first memory cell, data writing is performed for the first memory cell, the data of the first memory cell is first-determined by first reference threshold voltage, when data of the first memory cell is an insufficiency as a consequence of the first determination, rewriting of data for the first memory cell is performed after writing of data for the first memory cell, and after writing of data for the first memory cell is performed, writing of data for the second memory cell is performed, the data of the first memory cell is second-determined by second reference threshold voltage, when data of the first memory cell is an insufficiency as a consequence of the second determination, rewriting of data for the first memory cell is performed after writing of data for the second memory cell. The first reference threshold voltage is different from the second reference threshold voltage. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供可以减少错误读出频率并且可以减小数据破坏可能性的半导体存储器件的数据写入方法。解决方案：半导体存储器件的该数据写入方法具有与第一存储单元相邻的至少一个第二存储单元，对第一存储单元进行数据写入，第一存储单元的数据首先确定通过第一参考阈值电压，当作为第一确定的结果，第一存储器单元的数据不足时，在写入第一存储单元的数据之后，在写入用于第一存储单元的数据之后执行用于第一存储单元的数据的重写，执行第一存储单元，执行对第二存储单元的数据的写入，当第一存储单元的数据作为第二存储单元的结果不足时，第一存储单元的数据被第二参考阈值电压第二确定在写入第二存储单元的数据之后，执行第一存储器单元的数据的重写。第一参考阈值电压与第二参考阈值电压不同。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2004363329A Semiconductor storage device 有权
公开(公告)号：JP2004363329A
公开(公告)日：2004-12-24
申请号：JP2003160118
申请日：2003-06-04
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , AIDA AKIRA , TANAKA MASAYUKI
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/148 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0483 , H01L27/115 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To achieve high-speed erasing of the MONOS memory cell of a semiconductor storage device. SOLUTION: The semiconductor storage device comprises the memory cell capable of electrically writing and erasing information. The memory cell comprises: a first gate insulating layer 4 consisting of an insulating film of a compound comprising at least silicon and oxygen; a first charge storage layer 5 which is in contact with the first gate insulating layer 4 and consists of a silicon nitride film, a silicon oxynitride film or an alumina film; a second insulating layer 61 which is thicker than the first gate insulating layer 4; a second charge storage layer 62 which is in contact with the second insulating layer 61; a gate insulating layer which is in contact with the second charge storage layer 62, and includes a third insulating layer 63 having a larger thickness than the first gate insulating layer 4; and a control electrode 7 formed on the third insulating layer 63. The first gate insulating layer 4 may be a silicon oxynitride film having more oxygen compositions than the first charge storage layer 5. The thicknesses of the second insulating layer 61 and the third insulating layer 63 may be larger than 3nm. The arrangement may be such that an acceptor impurity is added to the second charge storage layer 62. COPYRIGHT: (C)2005,JPO&NCIPI

7. 发明专利

JP2004039866A Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：JP2004039866A
公开(公告)日：2004-02-05
申请号：JP2002195005
申请日：2002-07-03
申请人： Toshiba Corp , 株式会社東芝
发明人： AIDA AKIRA , NOGUCHI MITSUHIRO , TANAKA MASAYUKI , SAIDA SHIGEHIKO
IPC分类号： H01L27/10 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11546
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of high performance wherein a MONOS type memory cell is formed on a semiconductor substrate and a method for manufacturing the device.
SOLUTION: This semiconductor device is provided with the semiconductor substrate, the memory cell which is formed on the semiconductor substrate and has a first gate insulating film of a laminate structure which contains a silicon nitride film turning to a charge storage layer, and a transistor which is formed on the semiconductor substrate and has a second gate insulating film. A source/drain diffusion layer of the memory cell is coated with a part of the first gate insulating film, and a metal silicide film is formed on a surface of a source/drain diffusion layer of the transistor.
COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2002358792A SEMICONDUCTOR STORAGE DEVICE 审中-公开
公开(公告)号：JP2002358792A
公开(公告)日：2002-12-13
申请号：JP2001383554
申请日：2001-12-17
申请人： TOSHIBA CORP
发明人： NOGUCHI MITSUHIRO , AIDA AKIRA , MATSUNAGA YASUHIKO
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device in which dispersion of read-out current caused by a data state of a non-selection memory cell and a position of a selection memory cell is reduced. SOLUTION: When data of a memory cell M0 in a NAND cell unit 20 is read out, read-out voltage Vr is given to a selection word line WL0, pass voltage Vread is given to non-selection word lines WL1-WL15, pass voltage Vread is given to a control gate line SSL driving a selection transistor S1 of a bit line BL side, voltage VGSL being lower than the pass voltage Vread is given to a selection gate line GSL driving a selection transistor 82 of a common source line SL side.

9. 发明专利

JP2002313967A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002313967A
公开(公告)日：2002-10-25
申请号：JP2001317620
申请日：2001-10-16
申请人： TOSHIBA CORP
发明人： AIDA AKIRA , NOGUCHI MITSUHIRO , HAZAMA HIROAKI
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/8234 , H01L21/8246 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where electric characteristics of a gate insulating film near an element isolation region are equal to those of a gate insulating film other than the element isolation region vicinity, and to provide a method for manufacturing the semiconductor device. SOLUTION: The semiconductor device has a semiconductor substrate 1, a shallow trench element isolation region 13 that is formed in a groove section provided in the semiconductor substrate 1, a source/drain region that is formed in the semiconductor substrate 1 and uses a pinching semiconductor substrate surface as a channel, gate insulating films 10, 11, and 12 that are formed on the semiconductor substrate and have film thicknesses being equal at the center section of the channel and a section being in contact with the shallow trench element isolation region, and gate electrodes 14 and 15 that are formed on the gate insulating films 10, 11, and 12.

10. 发明专利

JP2001244335A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2001244335A
公开(公告)日：2001-09-07
申请号：JP2000057334
申请日：2000-03-02
申请人： TOSHIBA CORP
发明人： AIDA AKIRA , ITO KATSUYA , MATSUZAKI KENJI , TSUNODA HIROAKI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/8247 , H01L23/52 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the semiconductor device which make it possible to obtain a good contact performance by minute contact. SOLUTION: An interlayer insulating film 15 is formed on a semiconductor substrate 11 on which a transistor is formed, and on the top of the interlayer, wiring 18 is formed. As for contact hole 16 for connecting the wiring 18 to a diffused layer 14, an aspect ratio is 3 or higher, and a polycrystalline silicon layer 17 is buried in this contact hole 16 flatly. The polycrystalline silicon layer 17 consists of a first deposition layer of the polycrystalline silicon, which adsorbs impurity, and a second deposition layer of polycrystalline silicon layer, which is heat treated to make impurity distribution uniform ahead of etching back by CDE.

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