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1. 发明专利

JP2014127641A Memory device 有权
标题翻译：内存设备
公开(公告)号：JP2014127641A
公开(公告)日：2014-07-07
申请号：JP2012284823
申请日：2012-12-27
申请人： Toshiba Corp , 株式会社東芝
发明人： FURUHASHI HIRONOBU , KUNISHIMA IWAO , SHUDO SUSUMU , ASAO YOSHIAKI , SUDO TAKESHI
IPC分类号： H01L27/105 , G11C13/00 , H01L45/00
CPC分类号： G11C13/0002 , G11C11/5678 , G11C13/0004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/065 , H01L45/1233 , H01L45/144
摘要： PROBLEM TO BE SOLVED: To provide a memory device that has high recording density.SOLUTION: A memory device according to the present invention comprises an n (n is an integer of 2 or greater) number of resistance variation films connected to each other in series. Each resistance variation film is a superlattice film in which a plurality of pairs of first crystalline layer composed of a first compound and second crystalline layer composed of a second compound are alternately arranged in layers. In the n number of resistance variation films, the average compositions of all the resistance variation films or the arrangement periods of the first and second crystalline layers are different from each other.
摘要翻译：要解决的问题：提供具有高记录密度的存储器件。解决方案：根据本发明的存储器件包括串联连接的电阻变化膜的n（n为2以上的整数）数量的电阻变化膜。每个电阻变化膜是超晶格膜，其中由第一化合物构成的多对第一结晶层和由第二化合物构成的第二晶体层交替排列。在n个电阻变化膜中，所有电阻变化膜的平均组成或第一和第二结晶层的排列周期彼此不同。

2. 发明专利

JP2013041961A Resistance-changing memory, and method of manufacturing the same 审中-公开
标题翻译：电阻变化记忆及其制造方法
公开(公告)号：JP2013041961A
公开(公告)日：2013-02-28
申请号：JP2011177529
申请日：2011-08-15
申请人： Toshiba Corp , 株式会社東芝
发明人： HOSOYA KEIJI , SHUDO SUSUMU , KAJIYAMA TAKESHI
IPC分类号： H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To reduce the area of a chip.SOLUTION: A magnetic random access memory comprises: a first diffusion layer 17a formed on a device region 10a of a memory cell unit; a first contact CB1 connected with the first diffusion layer; a first lower electrode layer 21a formed on the first contact; a first resistance-changing layer 22a formed on the first lower electrode layer; and a first upper electrode layer 23a. The magnetic random access memory further comprises, in a peripheral circuit unit: second to fourth diffusion layers 17d, 17e formed in different device regions; second to fourth contacts CS1, CS2 connected with the second to fourth diffusion layers; and a second lower electrode layer 21b, a second resistance-changing layer 22b, and a second upper electrode layer 23b, which are formed to be coincident in height with the first lower electrode layer, the first resistance-changing layer, and the first upper electrode layer respectively. The second lower electrode layer functions as a first local wiring line L1 for connecting between the second and third contacts.
摘要翻译：要解决的问题：减少芯片的面积。解决方案：磁性随机存取存储器包括：形成在存储单元单元的器件区域10a上的第一扩散层17a; 与第一扩散层连接的第一触点CB1; 形成在第一触点上的第一下电极层21a; 形成在第一下电极层上的第一电阻变化层22a; 和第一上电极层23a。磁性随机存取存储器还包括在外围电路单元中：形成在不同器件区域中的第二至第四扩散层17d，17e; 与第二至第四扩散层连接的第二至第四触点CS1，CS2; 以及形成为与第一下电极层，第一电阻变化层和第一上电极层高度重合的第二下电极层21b，第二电阻变化层22b和第二上电极层23b 电极层。第二下电极层用作连接第二和第三触点之间的第一局部布线L1。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2011233835A Semiconductor memory and method of manufacturing the same 审中-公开
标题翻译：半导体存储器及其制造方法
公开(公告)号：JP2011233835A
公开(公告)日：2011-11-17
申请号：JP2010105450
申请日：2010-04-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KANAYA HIROYUKI , KOYAMA YUKINORI , SHUDO SUSUMU , SUGIURA KUNIAKI
IPC分类号： H01L27/105 , H01L21/768 , H01L21/8246 , H01L27/10 , H01L43/08
CPC分类号： H01L27/228 , H01L21/76897 , H01L43/12
摘要： PROBLEM TO BE SOLVED: To provide a high-reliability semiconductor memory having improved flatness of a top surface of a contact plug located under a memory element.SOLUTION: The semiconductor memory comprises: a semiconductor substrate; a plurality of switching transistors provided on the semiconductor substrate; a contact plug that is buried between two adjacent switching transistors, is isolated from each gate of the two adjacent switching transistors and electrically connected to sources or drains of the two adjacent switching transistors, and whose top surface is located at a higher position than the top surfaces of the switching transistors; a memory element storing data, which is formed on a top surface of the contact plug; and wiring provided on the memory element.
摘要翻译：要解决的问题：提供一种高可靠性半导体存储器，其具有改善位于存储元件下方的接触插塞的顶表面的平坦度。半导体存储器包括：半导体衬底; 设置在所述半导体基板上的多个开关晶体管; 埋在两个相邻开关晶体管之间的接触插塞与两个相邻的开关晶体管的每个栅极隔离，并且电连接到两个相邻开关晶体管的源极或漏极，并且其顶表面位于比顶部更高的位置开关晶体管的表面; 存储数据的存储元件，其形成在所述接触插塞的顶表面上; 以及设置在存储元件上的布线。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2010079953A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010079953A
公开(公告)日：2010-04-08
申请号：JP2008244383
申请日：2008-09-24
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/105
CPC分类号： G11C11/22 , H01L27/11504 , H01L27/11507
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device of which the leak current at the off time does not increase even though a block selection part is micronized, without lowering a performance of a memory cell.
SOLUTION: The semiconductor memory device includes: a plurality of cell blocks constituted in such a manner that a plurality of memory cells are connected in series, which include ferroelectric capacitors and cell transistors mutually connected in parallel; a plurality of word lines connected to gates of the plurality of cell transistors; a plurality of block selection parts including enhancement type transistors and depletion type transistors mutually connected in series; a plurality of bit lines connected to one ends of the plurality of cell blocks through the plurality of block selection parts; and a plurality of plate lines connected to another ends of the plurality of cell blocks. It has such a feature that a gate length of the enhancement type transistor is longer than a gate length of the depletion type transistor.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供即使块选择部分被微粉化，其关闭时的泄漏电流也不会增加的半导体存储器件，而不降低存储单元的性能。解决方案：半导体存储器件包括：以使多个存储单元串联连接的方式构成的多个单元块，其中包括并联连接的铁电电容器和单元晶体管; 连接到所述多个单元晶体管的栅极的多个字线; 多个块选择部分，包括串联连接的增强型晶体管和耗尽型晶体管; 通过所述多个块选择部分连接到所述多个单元块的一端的多个位线; 以及连接到所述多个单元块的另一端的多个板线。其特征在于，增强型晶体管的栅极长度比耗尽型晶体管的栅极长度长。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009187647A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2009187647A
公开(公告)日：2009-08-20
申请号：JP2008029503
申请日：2008-02-08
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： G11C29/12 , G11C11/22
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that applies voltage to a plurality of transistors at the same time and reduces time for a reliability test in the semiconductor memory device which is configured by connecting in series a plurality of memory cells configured with ferroelectric capacitors and transistors.
SOLUTION: The semiconductor memory device has a memory block which is configured by connecting in series a plurality of memory cells configured by connecting both electrodes of the ferroelectric capacitors to sources and drains of the transistors, a plurality of word lines connected to gates of the transistors of the memory cells, respectively, a plate line connected to one end of the memory block, a bit line connected to the other end of the memory block via a switching element for block selection and a control circuit that controls the plurality of transistors in the memory block and the switching element for block selection to apply voltage to two or more of the plurality of ferroelectric capacitors at the same time.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体存储器件，其同时对多个晶体管施加电压，并且通过将多个存储单元串联连接而构成的半导体存储器件中的可靠性测试时间缩短配置有铁电电容和晶体管。解决方案：半导体存储器件具有存储块，其通过将强电介质电容器的两个电极连接到晶体管的源极和漏极而构成的多个存储单元串联连接，多个字线连接到栅极存储单元的晶体管分别连接到存储块的一端的板线，经由用于块选择的开关元件连接到存储块的另一端的位线，以及控制电路，存储块中的晶体管和用于块选择的开关元件同时向多个铁电电容器中的两个或更多个施加电压。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008047760A Ferroelectric memory device and its manufacturing method 有权
标题翻译：电磁存储器件及其制造方法
公开(公告)号：JP2008047760A
公开(公告)日：2008-02-28
申请号：JP2006223228
申请日：2006-08-18
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： H01L21/8246 , H01L27/105
CPC分类号： H01L28/91 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a ferroelectric memory device in which cells are micro-fabricated by a simple production step.
SOLUTION: The method for manufacturing the ferroelectric memory device comprises the steps of: forming a ferroelectric layer 14 on a semiconductor substrate 10; forming a first hard mask layer 16 on the ferroelectric layer 14; forming a second hard mask layer 17 on the first hard mask layer 16; etching the second hard mask layer 17, the first hard mask layer 16, and the ferroelectric layer 14, in a direction perpendicular to a main surface of the substrate to form a plurality of trenches for an element isolation which are in parallel arranged; and forming electrode layers 15-1, 15-2 which are isolated on a side wall facing the trench of the ferroelectric layer 14 and the second hard mask layer 17, respectively.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过简单的生产步骤微电池制造铁电存储器件的方法。解决方案：制造铁电存储器件的方法包括以下步骤：在半导体衬底10上形成铁电层14; 在铁电层14上形成第一硬掩模层16; 在第一硬掩模层16上形成第二硬掩模层17; 在垂直于基板的主表面的方向上蚀刻第二硬掩模层17，第一硬掩模层16和铁电层14，以形成多个平行排列的用于元件隔离的沟槽; 以及分别在与铁电层14和第二硬掩模层17的沟槽相对的侧壁上分离的电极层15-1,15-2。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2006352005A FERROELECTRIC STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：JP2006352005A
公开(公告)日：2006-12-28
申请号：JP2005179172
申请日：2005-06-20
申请人： TOSHIBA CORP
发明人： SHUDO SUSUMU
IPC分类号： H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To achieve the microfabrication of cells in a ferroelectric storage device. SOLUTION: This ferroelectric storage device is provided with a transistor 50 formed on a substrate 10 and a ferroelectric capacitor formed at the upper part through a first inter-layer film 60, and arranged so that a direction connecting electrodes 100 can follow the channel lengthwise direction of the transistor 50. A groove configured of a sacrificial film is used when forming a ferroelectric film 90, so that the microfabrication of the ferroelectric capacitor can be attained by setting a distance between electrodes 100 of the capacitor as not more than working dimensions by lithography. COPYRIGHT: (C)2007,JPO&INPIT

8. 发明专利

JP2005196924A Semiconductor integrated circuit apparatus, and bit line capacity adjustment method using the apparatus 审中-公开
标题翻译：半导体集成电路设备和使用设备的位线容量调整方法
公开(公告)号：JP2005196924A
公开(公告)日：2005-07-21
申请号：JP2004004554
申请日：2004-01-09
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： G11C11/22 , G11C29/02 , G11C29/12 , H01L21/8246 , H01L27/105 , G11C29/00
CPC分类号： G11C29/025 , G11C7/12 , G11C11/22 , G11C29/02 , G11C29/028 , G11C2029/5002
摘要： PROBLEM TO BE SOLVED: To optimize bit line capacity after manufacturing a device.
SOLUTION: A semiconductor integrated circuit apparatus is provided with: a first transistor Trc having a first source/drain and a first gate; a ferroelectric capacitor Cf connected to one end of the first source/drain; a bit line BL connected to the other end of the source/drain; one or more capacitors C connected to the bit line BL; and a control circuit 11 connecting or disconnecting the capacitor C to or from the bit line Bl electrically.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在制造设备后优化位线容量。解决方案：半导体集成电路装置具有：具有第一源/漏极和第一栅极的第一晶体管Trc; 连接到第一源极/漏极的一端的铁电电容器Cf; 连接到源极/漏极的另一端的位线BL; 连接到位线BL的一个或多个电容器C; 以及将电容器C与位线B1电连接或断开的控制电路11。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2001358316A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001358316A
公开(公告)日：2001-12-26
申请号：JP2001188538
申请日：2001-06-21
申请人： TOSHIBA CORP
发明人： MOCHIZUKI HIROSHI , KANETANI HIROYUKI , KUNISHIMA IWAO , SHUDO SUSUMU , OKUWADA HISAMI , HIDAKA OSAMU
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To form a dense ferroelectric film having high reliability in the case of manufacturing an FRAM using a ferroelectric substance as an insulating film of an information storage capacitor. SOLUTION: A method for manufacturing a semiconductor device comprises the steps sequentially forming a first electrode; a dielectric film and a second electrode in the case of forming a capacitor using the dielectric film made of a composite oxide film between a pair of electrodes, and laminating an insulating oxide film and a wiring layer on the capacitor and quickly heat treating at a temperature rising speed of 10 deg.C/s or more at a reduce pressure of 0.5×133.322 to 500×133.322 Pa between a first electrode forming step and a dielectric film forming step, between the dielectric film forming step and a second electrode forming step, or after the second electrode forming step.

10. 发明专利

JP2000036568A SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000036568A
公开(公告)日：2000-02-02
申请号：JP20297998
申请日：1998-07-17
申请人： TOSHIBA CORP
发明人： SHUDO SUSUMU
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To flatly form the wiring layer as the first layer also facilitating the making and burying-in contact holes connecting the wiring layers to the semiconductor substrate surface. SOLUTION: In a semiconductor memory, an upper electrode 23 of a FRAM (ferodielectric memory) capacitor is connected to the diffused layer 14 on the surface of a semiconductor substrate 11 through the intermediary of a contact hole 35, a wiring layer 34 as the second layer, another contact hole 33, another wiring layer 28 as the first layer, and the other contact hole 25. Accordingly, the wiring layer 28 of the first layer is formed on the same level as that of the FRAM capacitor. Through these procedures, the depth of the contact hole connecting the wiring layer 28 as the first layer to the surface of the semiconductor substrate 11 is shallowed for decreasing the aspect ratio. Resultantly, the formation and burying-in of the contact holes can be facilitated, thereby making feasible of miniaturizing the semiconductor memory.

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