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31. 发明授权

US06661687B1 Cam circuit with separate memory and logic operating voltages 有权
标题翻译：凸轮电路具有独立的存储器和逻辑工作电压
公开(公告)号：US06661687B1
公开(公告)日：2003-12-09
申请号：US10350991
申请日：2003-01-23
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G11C14/00 , G11C15/04 , G11C15/043
摘要： A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control at least some of the logic portions of each CAM circuit. The CAM cell memory portion includes a memory (e.g., SRAM) cell controlled by a word line to store data values transmitted on complementary bit lines. The CAM cell logic portion includes a comparator that compares the stored data values with an applied data value transmitted on complementary data lines, and discharges a match line when the stored data value differs from the applied data value. The memory cell is driven using the relatively high memory operating voltage (e.g., 2.5 Volts) such that the stored charge resists soft errors. The complementary data lines and match line used to operate the comparator are driven using the relatively low logic operating voltage (e.g., 1.2 Volts) to conserve power.
摘要翻译： CAM电路利用相对高的工作电压来控制每个CAM单元的存储器部分，以及相对低的工作电压来控制每个CAM电路的至少一些逻辑部分。 CAM单元存储器部分包括由字线控制的存储器（例如，SRAM）单元，以存储在互补位线上传输的数据值。 CAM单元逻辑部分包括比较器，用于比较存储的数据值和互补数据线上传输的应用数据值，并且当存储的数据值与应用的数据值不同时，对其进行放电。使用相对高的存储器工作电压（例如，2.5伏特）来驱动存储器单元，使得存储的电荷抵抗软错误。用于操作比较器的补充数据线和匹配线使用相对较低的逻辑工作电压（例如，1.2伏特）来驱动以节省功率。

32. 发明授权

US06657878B2 Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same 有权
标题翻译：具有可靠列冗余特性的内容可寻址存储器（CAM）器件及其操作方法
公开(公告)号：US06657878B2
公开(公告)日：2003-12-02
申请号：US10084842
申请日：2002-02-27
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00 , G11C29/816
摘要： Content addressable memory (CAM) devices provide improved reliability by inhibiting disabled CAM cells within defective (or unused redundant columns) from contributing to either sustained or intermittent look-up errors when the CAM device is operated in an intended application. The improved reliability may be achieved in volatile CAM devices by configuring (e.g., programming) each column driver that is associated with a CAM array having a defective column therein to preserve intentionally written data and/or mask values of the disabled CAM cells across repeated power reset events.
摘要翻译：内容可寻址存储器（CAM）器件通过禁止在缺陷（或未使用的冗余列）中的禁用的CAM单元在CAM设备在预期应用中操作时造成持续或间歇查找错误而提供改进的可靠性。通过配置（例如，编程）与其中具有缺陷列的CAM阵列相关联的每个列驱动器，可以在易失性CAM设备中实现改进的可靠性，以保留有效地写入的数据和/或禁用的CAM单元的重复功率的屏蔽值复位事件。

33. 发明授权

US06505271B1 Increasing priority encoder speed using the most significant bit of a priority address 有权
标题翻译：使用优先级地址的最高有效位来提高编码器速度
公开(公告)号：US06505271B1
公开(公告)日：2003-01-07
申请号：US09439968
申请日：1999-11-12
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G06F1206
CPC分类号： G11C15/00 , G06F7/74
摘要： A method of generating a priority address using a priority encoder that includes the steps of: (1) providing a plurality of match signals from a CAM cell memory array to the priority encoder, (2) generating a most significant address bit of the priority address in response to a first set of the match signals, and (3) generating a least significant address bit of the priority address in response to the most significant address bit and a second set of the match signals. In one embodiment, step (3) is implemented by splitting the determination of the least significant address bit into two separate determinations, and the using the most significant address bit to select the result of one of these two separate determinations. Using the most significant address bit to help determine the least significant address bit significantly increases the speed of determining the least significant address bit, thereby increasing the overall speed of the priority encoder. Another embodiment includes a priority encoder that includes a first address generator for generating the most significant address bit in response to the first set of match signals, and a second address generator for generating the least significant address bit in response to the second set of match signals and the most significant address bit.
摘要翻译：一种使用优先级编码器生成优先级地址的方法，该优先编码器包括以下步骤：（1）从CAM单元存储器阵列向优先编码器提供多个匹配信号，（2）产生优先地址的最高有效地址位响应于第一组匹配信号，以及（3）响应于最高有效地址位和第二组匹配信号产生优先级地址的最低有效地址位。在一个实施例中，通过将最低有效地址位的确定分成两个单独的确定来实现步骤（3），并且使用最高有效地址位来选择这两个单独确定之一的结果。使用最高有效地址位来帮助确定最低有效地址位显着增加确定最低有效地址位的速度，从而提高优先级编码器的总速度。另一个实施例包括优先编码器，其包括响应于第一组匹配信号产生最高有效地址位的第一地址发生器，以及响应于第二组匹配信号产生最低有效地址位的第二地址发生器和最重要的地址位。

34. 发明授权

US06262907B1 Ternary CAM array 有权
标题翻译：三元CAM阵列
公开(公告)号：US06262907B1
公开(公告)日：2001-07-17
申请号：US09574747
申请日：2000-05-18
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1500
CPC分类号： G11C15/046 , G11C15/04 , G11C15/043
摘要： A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, a comparison element that is used to compare the stored value with an applied data value, and a discharge element that is coupled between the discharge line and the match line. During operation, when the applied data value matches the stored value, the discharge element de-couples the discharge line from the match line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the discharge elements couple the discharge line to the match line, thereby discharging the match line to the discharge line. By discharging the match line to the discharge line instead of the bit lines of the CAM array, the size of the CAM array is not limited by the length bit lines. Because the voltage on the match line is sensed to determine the match/no-match condition of a CAM cell, the match line does not need to be completely discharged.
摘要翻译：公开了一种包括挥发性或非挥发性三元CAM单元的CAM阵列，其通过特殊的放电线（例如，低匹配线）而不是通过位线而排出其相关匹配线。每个三元CAM单元包括用于存储数据位值的一对存储元件，用于将存储的值与应用的数据值进行比较的比较元件，以及耦合在放电线和匹配线。在操作期间，当所应用的数据值与存储的值匹配时，放电元件将放电线与匹配线解耦（即，匹配线上的高电压保持为高）。相反，当所施加的数据值与存储值不匹配时，放电元件将放电线耦合到匹配线，从而将匹配线放电到放电线。通过将匹配线排放到放电线而不是CAM阵列的位线，CAM阵列的大小不受长度位线的限制。由于感测匹配线上的电压以确定CAM单元的匹配/不匹配条件，所以匹配线不需要被完全放电。

35. 发明授权

US06256216B1 Cam array with minimum cell size 有权
标题翻译：具有最小单元尺寸的凸轮阵列
公开(公告)号：US06256216B1
公开(公告)日：2001-07-03
申请号：US09574744
申请日：2000-05-18
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1500
CPC分类号： G11C15/046
摘要： A CAM array includes non-volatile ternary CAM cells that use access transistors to easily read from and write to the non-volatile transistors. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, and an access element that is used during CAM array operation. During a comparison operation, when the applied data value matches the stored value, the storage elements de-couple the match line from a discharging bit line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the storage elements couple the match line to a discharging bit line, thereby discharging the match line.
摘要翻译： CAM阵列包括使用存取晶体管容易地读取和写入非易失性晶体管的非易失性三元CAM单元。每个三元CAM单元包括用于存储数据位值的一对存储元件，以及在CAM阵列操作期间使用的存取元件。在比较操作期间，当所应用的数据值与存储的值匹配时，存储元件将匹配线与放电位线去耦（即，匹配线上的高电压保持为高）。相反，当所应用的数据值与存储的值不匹配时，存储元件将匹配线耦合到放电位线，从而放电匹配线。

36. 发明授权

US6101116A Six transistor content addressable memory cell 有权
标题翻译：六个晶体管内容可寻址存储单元
公开(公告)号：US6101116A
公开(公告)日：2000-08-08
申请号：US345224
申请日：1999-06-30
申请人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Henry Yeh
发明人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Henry Yeh
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A six transistor content addressable memory (CAM) cell that prevents disturb of non-written rows during a write operation. The CAM cell comprises an SRAM cell having a pair of cross-coupled inverters and a pair of access transistors. The SRAM cell stores a data value at the output node of one of the inverters and an inverse data value at the output node of the other one of the inverters. An access transistor is connected between each output node and a match line. The match line is connected across the access transistors such that the match line is coupled to the output nodes of the inverters when the access transistors are turned on. Data lines are connected to the gates of the access transistors, and are coupled to receive a data value and an inverse data value. The 6-T CAM cell of this embodiment can be coupled to a plurality of identical 6-T CAM cells to form an array. Each row of CAM cells is coupled to the same match line. Data values are written to and compared with data values stored within each CAM cell. A match condition is sensed on the match line. This 6-T CAM cell is therefore available for reliable use in a storage array. An additional benefit of the 6-T CAM cell is the small cell area due to the small number of transistors.
摘要翻译：六个晶体管内容可寻址存储器（CAM）单元，用于防止写入操作期间非写入行的干扰。 CAM单元包括具有一对交叉耦合的反相器和一对存取晶体管的SRAM单元。 SRAM单元在其中一个逆变器的输出节点处存储数据值，另一个反相器的输出节点存储逆数据值。在每个输出节点和匹配线之间连接一个存取晶体管。匹配线连接在存取晶体管两端，使得当存取晶体管导通时，匹配线耦合到反相器的输出节点。数据线连接到存取晶体管的栅极，并被耦合以接收数据值和逆数据值。该实施例的6-T CAM单元可以耦合到多个相同的6-T CAM单元以形成阵列。每一行CAM单元被耦合到相同的匹配线。将数据值写入并与存储在每个CAM单元内的数据值进行比较。在匹配线上感测到匹配条件。因此，这种6-T CAM单元可用于存储阵列中的可靠使用。由于晶体管的数量少，6-T CAM单元的另外一个好处是小区域。

37. 发明授权

US5079447A BiCMOS gates with improved driver stages 失效
标题翻译： BiCMOS门与改进的驱动阶段
公开(公告)号：US5079447A
公开(公告)日：1992-01-07
申请号：US496469
申请日：1990-03-20
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： H03K19/003 , H03K19/013 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/00307 , H03K19/00376 , H03K19/0136
摘要： In accordance with the present invention, an improved output driver stage for a BiCMOS logic gate is provided by including a clamping transistor. Such clamping transistor avoids, in the pull-up bipolar transistor, both degradation of current gain and emitter-to-collector breakdown.
摘要翻译：根据本发明，通过包括钳位晶体管来提供用于BiCMOS逻辑门的改进的输出驱动级。这种钳位晶体管避免了在上拉双极晶体管中，电流增益和发射极到集电极击穿的降低。

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