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1. 发明授权

US6101116A Six transistor content addressable memory cell 有权
标题翻译：六个晶体管内容可寻址存储单元
公开(公告)号：US6101116A
公开(公告)日：2000-08-08
申请号：US345224
申请日：1999-06-30
申请人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Henry Yeh
发明人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Henry Yeh
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A six transistor content addressable memory (CAM) cell that prevents disturb of non-written rows during a write operation. The CAM cell comprises an SRAM cell having a pair of cross-coupled inverters and a pair of access transistors. The SRAM cell stores a data value at the output node of one of the inverters and an inverse data value at the output node of the other one of the inverters. An access transistor is connected between each output node and a match line. The match line is connected across the access transistors such that the match line is coupled to the output nodes of the inverters when the access transistors are turned on. Data lines are connected to the gates of the access transistors, and are coupled to receive a data value and an inverse data value. The 6-T CAM cell of this embodiment can be coupled to a plurality of identical 6-T CAM cells to form an array. Each row of CAM cells is coupled to the same match line. Data values are written to and compared with data values stored within each CAM cell. A match condition is sensed on the match line. This 6-T CAM cell is therefore available for reliable use in a storage array. An additional benefit of the 6-T CAM cell is the small cell area due to the small number of transistors.
摘要翻译：六个晶体管内容可寻址存储器（CAM）单元，用于防止写入操作期间非写入行的干扰。 CAM单元包括具有一对交叉耦合的反相器和一对存取晶体管的SRAM单元。 SRAM单元在其中一个逆变器的输出节点处存储数据值，另一个反相器的输出节点存储逆数据值。在每个输出节点和匹配线之间连接一个存取晶体管。匹配线连接在存取晶体管两端，使得当存取晶体管导通时，匹配线耦合到反相器的输出节点。数据线连接到存取晶体管的栅极，并被耦合以接收数据值和逆数据值。该实施例的6-T CAM单元可以耦合到多个相同的6-T CAM单元以形成阵列。每一行CAM单元被耦合到相同的匹配线。将数据值写入并与存储在每个CAM单元内的数据值进行比较。在匹配线上感测到匹配条件。因此，这种6-T CAM单元可用于存储阵列中的可靠使用。由于晶体管的数量少，6-T CAM单元的另外一个好处是小区域。

2. 发明授权

US07545660B1 Method and apparatus for CAM with reduced cross-coupling interference 有权
标题翻译：具有降低的交叉耦合干扰的CAM的方法和装置
公开(公告)号：US07545660B1
公开(公告)日：2009-06-09
申请号：US11931868
申请日：2007-10-31
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/02
摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.
摘要翻译：已经公开了一种具有减小的交叉耦合干扰的CAM的方法和装置。

3. 发明授权

US06781857B1 Content addressable memory (CAM) devices that utilize multi-port CAM cells and control logic to support multiple overlapping search cycles that are asynchronously timed relative to each other 有权
标题翻译：使用多端口CAM单元和控制逻辑的内容可寻址存储器（CAM）设备来支持相对于彼此异步定时的多个重叠的搜索周期
公开(公告)号：US06781857B1
公开(公告)日：2004-08-24
申请号：US10306799
申请日：2002-11-27
申请人： Chuen-Der Lien , Chau-Chin Wu , Mark Baumann
发明人： Chuen-Der Lien , Chau-Chin Wu , Mark Baumann
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00
摘要： A CAM device includes an array of multi-compare port CAM cells therein. The CAM cells are configured to support concurrent search operations between multiple distinct search words and entries within the rows of the CAM array. These concurrent search operations may be performed in-sync with respective clock signals that are asynchronous relative to each other.
摘要翻译： CAM设备包括其中的多比较端口CAM单元阵列。 CAM单元被配置为支持多个不同搜索词和CAM阵列的行内的条目之间的并发搜索操作。这些并发搜索操作可以与相对于彼此异步的各个时钟信号同步执行。

4. 再颁专利

USRE39227E1 Content addressable memory (CAM) arrays and cells having low power requirements 有权
标题翻译：内容可寻址存储器（CAM）阵列和具有低功率要求的单元
公开(公告)号：USRE39227E1
公开(公告)日：2006-08-08
申请号：US10403581
申请日：2003-03-31
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a VCC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the VCC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the VCC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the VCC supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match scan line prior to a compare operation. If the data value stored in the CAM cell does not match the comparison data value, the match sense line is pulled down. The signal swing of the match sense line is smaller than the VCC supply voltage. For example, the signal swing on the match sense line can be as low as one transistor threshold voltage.
摘要翻译：一种内容可寻址存储器（CAM）单元，其包括响应于V CC电源电压工作的静态随机存取存储器（SRAM）单元。耦合到SRAM单元的第一组位线用于将数据值传送到SRAM单元和从SRAM单元传送数据值。在第一组位线上发送的信号具有等于V CC电源电压的信号摆幅。第二组位线被耦合以接收比较数据值。在第二组位线上发送的信号具有小于V CC电源电压的信号摆幅。例如，第二组位线上的信号摆幅可以低至两个晶体管阈值电压。第二组位线被供给电压偏压，该电源电压小于V CC电源电压。提供了一种传感器电路，用于将存储在CAM单元中的数据值与比较数据值进行比较。在比较操作之前，传感器电路对匹配扫描线进行预充电。如果存储在CAM单元中的数据值与比较数据值不匹配，则下拉匹配检测线。匹配检测线的信号摆幅小于V CC电源电压。例如，匹配检测线上的信号摆幅可以低至一个晶体管阈值电压。

5. 发明授权

US06512685B1 CAM circuit with separate memory and logic operating voltages 有权
标题翻译： CAM电路具有独立的存储器和逻辑工作电压
公开(公告)号：US06512685B1
公开(公告)日：2003-01-28
申请号：US10164981
申请日：2002-06-06
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1504
CPC分类号： G11C15/00 , G11C14/00 , G11C15/04 , G11C15/043
摘要： A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control the logic portion of each CAM cell. The CAM cell memory portion includes a memory (e.g., SRAM) cell controlled by a word line to store data values transmitted on complementary bit lines. The CAM cell logic portion includes a comparator that compares the stored data values with an applied data value transmitted on complementary data lines, and discharges a match line when the stored data value differs from the applied data value. The memory cell is driven using the relatively high memory operating voltage (e.g., 2.5 Volts) such that the stored charge resists soft errors. The complementary data lines and match line used to operate the comparator are driven using the relatively low logic operating voltage (e.g., 1.2 Volts) to conserve power.
摘要翻译： CAM电路利用相对较高的工作电压来控制每个CAM单元的存储器部分，以及相对低的工作电压来控制每个CAM单元的逻辑部分。 CAM单元存储器部分包括由字线控制的存储器（例如，SRAM）单元，以存储在互补位线上传输的数据值。 CAM单元逻辑部分包括比较器，用于比较存储的数据值和互补数据线上传输的应用数据值，并且当存储的数据值与应用的数据值不同时，对其进行放电。使用相对高的存储器工作电压（例如，2.5伏特）来驱动存储器单元，使得存储的电荷抵抗软错误。用于操作比较器的补充数据线和匹配线使用相对较低的逻辑工作电压（例如，1.2伏特）来驱动以节省功率。

6. 发明授权

US06421265B1 DRAM-based CAM cell using 3T or 4T DRAM cells 有权
标题翻译：基于DRAM的CAM单元使用3T或4T DRAM单元
公开(公告)号：US06421265B1
公开(公告)日：2002-07-16
申请号：US09816742
申请日：2001-03-22
申请人： Chuen-Der Lien , Chau-Chin Wu , Ta-Ke Tien
发明人： Chuen-Der Lien , Chau-Chin Wu , Ta-Ke Tien
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A CAM cell including three-transistor (3T) or four-transistor (4T) DRAM cells. Data is stored using intrinsic capacitance of each 3T or 4T DRAM cell, and is applied to the gate terminal of a pull-down transistor. Read operations are performed in the 3T and 4T DRAM cells without disturbing the stored data value by applying the stored data value to the gate terminal of a pull-down transistor and detecting the operating state (i.e., turned on or turned off) of a pull-down transistor, thereby avoiding the charge sharing problems associated with 1T DRAM cells.
摘要翻译：包括三晶体管（3T）或四晶体管（4T）DRAM单元的CAM单元。使用每个3T或4T DRAM单元的固有电容来存储数据，并且被施加到下拉晶体管的栅极端子。通过将存储的数据值应用于下拉晶体管的栅极端子并检测拉动的操作状态（即，导通或关闭），在3T和4T DRAM单元中执行读操作，而不会干扰存储的数据值降低晶体管，从而避免与1T DRAM单元相关的电荷共享问题。

7. 发明授权

US06215708B1 Charge pump for improving memory cell low VCC performance without increasing gate oxide thickness 有权
标题翻译：电荷泵用于提高存储单元的低VCC性能，而不增加栅极氧化物厚度
公开(公告)号：US06215708B1
公开(公告)日：2001-04-10
申请号：US09164450
申请日：1998-09-30
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1604
CPC分类号： G11C5/145 , G11C8/08 , G11C11/4085
摘要： A memory circuit that operates in response to a VCC supply voltage and a ground voltage is provided. The memory circuit includes a word line voltage generation circuit that generates a fixed word line voltage. The fixed word line voltage is selectively applied to word lines of the memory circuit. The word line voltage generation circuit generates the fixed word line voltage for all values of the VCC supply voltage between the minimum VCC supply voltage and the maximum VCC supply voltage. The fixed word line voltage is referenced to the ground voltage, rather than the VCC supply voltage. Because the ground voltage does not vary, the boosted word line voltage of the present invention can be controlled more precisely than prior art boosted word line voltages, which are referenced to the VCC supply voltage. This improved control enables the boosted word line voltage to be fixed for the entire range of the VCC supply voltage. This improved control also enables the boosted word line voltage to be selected to optimize the operating and design characteristics of the memory circuit.
摘要翻译：提供响应于VCC电源电压和接地电压工作的存储器电路。存储电路包括产生固定字线电压的字线电压产生电路。固定字线电压被选择性地施加到存储器电路的字线。字线电压产生电路为VCC电源电压的最小VCC电源电压和最大VCC电源电压之间的所有值产生固定字线电压。固定字线电压参考地电压，而不是VCC电源电压。因为接地电压没有变化，所以本发明的升压字线电压可以比参考VCC电源电压的现有技术的升压字线电压更精确地被控制。该改进的控制使得可以在VCC电源电压的整个范围内固定升压的字线电压。该改进的控制还使得可以选择提升的字线电压来优化存储器电路的操作和设计特性。

8. 发明授权

US07859876B1 Method and apparatus for CAM with reduced cross-coupling interference 有权
标题翻译：具有降低的交叉耦合干扰的CAM的方法和装置
公开(公告)号：US07859876B1
公开(公告)日：2010-12-28
申请号：US11765326
申请日：2007-06-19
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/02
摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.
摘要翻译：已经公开了一种具有减小的交叉耦合干扰的CAM的方法和装置。

9. 再颁专利

USRE41351E1 CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same 失效
标题翻译： CAM阵列，其中具有匹配线和低匹配线路连接的CAM单元及其操作方法
公开(公告)号：USRE41351E1
公开(公告)日：2010-05-25
申请号：US10106420
申请日：2002-03-26
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C15/04 , G11C15/043
摘要： A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, a comparison element that is used to compare the stored value with an applied data value, and a discharge element that is coupled between the discharge line and the match line. During operation, when the applied data value matches the stored value, the discharge element de-couples the discharge line from the match line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the discharge elements couple the discharge line to the match line, thereby discharging the match line to the discharge line. By discharging the match line to the discharge line instead of the bit lines of the CAM array, the size of the CAM array is not limited by the length bit lines. Because the voltage on the match line is sensed to determine the match/no-match condition of a CAM cell, the match line does not need to be completely discharged.
摘要翻译：公开了一种包括挥发性或非挥发性三元CAM单元的CAM阵列，其通过特殊的放电线（例如，低匹配线）而不是通过位线而排出其相关匹配线。每个三元CAM单元包括用于存储数据位值的一对存储元件，用于将存储的值与应用的数据值进行比较的比较元件，以及耦合在放电线和匹配线。在操作期间，当所应用的数据值与存储的值匹配时，放电元件将放电线与匹配线解耦（即，匹配线上的高电压保持为高）。相反，当所施加的数据值与存储值不匹配时，放电元件将放电线耦合到匹配线，从而将匹配线放电到放电线。通过将匹配线排放到放电线而不是CAM阵列的位线，CAM阵列的大小不受长度位线的限制。由于感测匹配线上的电压以确定CAM单元的匹配/不匹配条件，所以匹配线不需要被完全放电。

10. 发明授权

US07304875B1 Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same 有权
标题翻译：支持背景BIST和BISR操作的内容可寻址内存（CAM）设备及其操作方法
公开(公告)号：US07304875B1
公开(公告)日：2007-12-04
申请号：US11184414
申请日：2005-07-19
申请人： Chuen Der Lien , Michael Miller , Chau-Chin Wu , Kee Park , Scott Yu-Fan Chu
发明人： Chuen Der Lien , Michael Miller , Chau-Chin Wu , Kee Park , Scott Yu-Fan Chu
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G06F11/1064 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/816 , G11C2029/1208
摘要： Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit. The control circuit, which is electrically coupled to the plurality of CAM array blocks, is configured to perform built-in self repair (BISR) of hard memory defects and/or compare logic defects in the plurality of CAM array blocks concurrently with operations to search entries in the plurality of CAM array blocks.
摘要翻译：搜索引擎设备包括其中具有多个CAM阵列块的内容可寻址存储器（CAM）核和控制电路。电耦合到多个CAM阵列块的控制电路被配置为与搜索操作同时执行硬存储器缺陷的内置自修复（BISR）和/或比较多个CAM阵列块中的逻辑缺陷多个CAM阵列块中的条目。

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