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31. 发明授权

US06791081B1 Method for determining pore characteristics in porous materials 失效
标题翻译：确定多孔材料孔隙特性的方法
公开(公告)号：US06791081B1
公开(公告)日：2004-09-14
申请号：US10109517
申请日：2002-03-27
申请人： Robert Matthew Ulfig , Suzette K. Pangrle , Alline F. Myers , Jeremias D. Romero
发明人： Robert Matthew Ulfig , Suzette K. Pangrle , Alline F. Myers , Jeremias D. Romero
IPC分类号： G01B528
CPC分类号： G01Q60/24 , G01N15/088 , Y10S977/852
摘要： A method for measuring porosity of nanoporous materials is provided using atomic force microscopy (AFM). A surface topology map with sub-atomic resolution is created using AFM wherein the pore shape and size can be determined by measuring the pores that intersect the top or fracture surface. For porous materials requiring more accurate measurements, small scan areas with slow scan speed and fine AFM tips are used and a general estimation on distribution can be made from a sample area.
摘要翻译：使用原子力显微镜（AFM）提供了一种测量纳米多孔材料孔隙率的方法。使用AFM创建具有亚原子分辨率的表面拓扑图，其中孔形状和尺寸可以通过测量与顶部或断裂面相交的孔来确定。对于需要更精确测量的多孔材料，使用扫描速度慢的微小扫描区域和精细的AFM尖端，并且可以从样品区域进行一般的分布估计。

32. 发明授权

US06713382B1 Vapor treatment for repairing damage of low-k dielectric 有权
标题翻译：用于修复低k电介质损伤的蒸气处理
公开(公告)号：US06713382B1
公开(公告)日：2004-03-30
申请号：US10059268
申请日：2002-01-31
申请人： Suzette K. Pangrle , Ecran Adem , Calvin Gabriel , Lynne A. Okada
发明人： Suzette K. Pangrle , Ecran Adem , Calvin Gabriel , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening having side surfaces through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The process also includes the step of replacing hydroxyl terminated ions on the side surfaces. This step of replacing the hydroxyl terminated ions can occur after the opening is formed or after the first barrier layer is etched. A semiconductor device produced by the method of manufacturing is also disclosed.
摘要翻译：一种制造半导体器件的方法包括形成第一层，在第一层上形成第一势垒层，在第一阻挡层上形成电介质层，形成通过介电层的侧表面的开口，蚀刻第一阻挡层，并用金属填充开口以形成第一金属特征。该方法还包括在侧表面上置换羟基封端的离子的步骤。取代羟基封端的离子的该步骤可以在形成开口之后或在第一阻挡层被蚀刻之后发生。还公开了通过制造方法制造的半导体器件。

33. 发明申请

US20120248607A1 Semiconductor die having fine pitch electrical interconnects 有权
标题翻译：具有细间距电互连的半导体管芯
公开(公告)号：US20120248607A1
公开(公告)日：2012-10-04
申请号：US13243877
申请日：2011-09-23
申请人： Keith Lake Barrie , Suzette K. Pangrle , Grant Villavicencio , Jeffrey S. Leal
发明人： Keith Lake Barrie , Suzette K. Pangrle , Grant Villavicencio , Jeffrey S. Leal
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L24/83 , H01L23/293 , H01L23/3185 , H01L24/05 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L2224/0345 , H01L2224/0346 , H01L2224/038 , H01L2224/0381 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05567 , H01L2224/05573 , H01L2224/05644 , H01L2224/05664 , H01L2224/1131 , H01L2224/11848 , H01L2224/13017 , H01L2224/1329 , H01L2224/133 , H01L2224/13311 , H01L2224/13313 , H01L2224/13347 , H01L2224/16145 , H01L2224/24051 , H01L2224/24105 , H01L2224/24146 , H01L2224/24226 , H01L2224/244 , H01L2224/245 , H01L2224/24992 , H01L2224/24997 , H01L2224/25175 , H01L2224/2919 , H01L2224/82009 , H01L2224/82039 , H01L2224/82101 , H01L2224/831 , H01L2225/06524 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/12042 , H01L2924/14 , H01L2924/0665 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.
摘要翻译：裸片在互连端附近在互连边缘附近具有互连焊盘，并且互连面的至少一部分由保形电介质涂层覆盖，其中在电介质涂层上的互连迹线与电介质的表面形成高界面角涂层。由于迹线具有高界面角度，互连材料横向渗出的趋势被减轻，并且避免了相邻迹线的接触或重叠。互连迹线包括可固化的导电互连材料; 也就是说，它包括可以以可流动形式施加的材料，然后固化或允许其固化以形成导电迹线。此外，一种方法包括在形成迹线之前，用CF 4等离子体处理对保形电介质涂层的表面进行处理。

34. 发明授权

US08089113B2 Damascene metal-insulator-metal (MIM) device 有权
标题翻译：大马士革金属绝缘子金属（MIM）器件
公开(公告)号：US08089113B2
公开(公告)日：2012-01-03
申请号：US11633929
申请日：2006-12-05
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L29/94 , H01L27/108
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1666
摘要： The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
摘要翻译：制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二导电体在开口处。

35. 发明申请

US20110272825A1 STACKED DIE ASSEMBLY HAVING REDUCED STRESS ELECTRICAL INTERCONNECTS 有权
标题翻译：具有减少应力电气互连的堆叠式电池组件
公开(公告)号：US20110272825A1
公开(公告)日：2011-11-10
申请号：US12939524
申请日：2010-11-04
申请人： Scott McGrath , Jeffrey S. Leal , Ravi Shenoy , Loreto Cantillep , Simon J. S. McElrea , Suzette K. Pangrle
发明人： Scott McGrath , Jeffrey S. Leal , Ravi Shenoy , Loreto Cantillep , Simon J. S. McElrea , Suzette K. Pangrle
IPC分类号： H01L23/522 , H01L21/56
CPC分类号： H01L21/563 , H01L23/3121 , H01L23/49805 , H01L23/562 , H01L24/06 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/82 , H01L25/0657 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/16225 , H01L2224/24011 , H01L2224/24051 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/73203 , H01L2224/76155 , H01L2224/82102 , H01L2225/06517 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2924/00
摘要： Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.
摘要翻译：公开了用于改进堆叠模具组件中的电互连的方法，并且公开了具有通过该方法形成的结构特征的堆叠模具组件。所得到的堆叠的模具组件的特征在于具有减小的电互连故障。

36. 发明授权

US08044387B1 Semiconductor device built on plastic substrate 有权
标题翻译：半导体器件内置塑料基板
公开(公告)号：US08044387B1
公开(公告)日：2011-10-25
申请号：US10885959
申请日：2004-07-07
申请人： Matthew S. Buynoski , Uzodinma Okoroanyanwu , Suzette K. Pangrle , Nicholas H. Tripsas
发明人： Matthew S. Buynoski , Uzodinma Okoroanyanwu , Suzette K. Pangrle , Nicholas H. Tripsas
IPC分类号： H01L35/24
CPC分类号： H01L51/0591 , G11C13/0016 , G11C2213/71 , H01L27/285 , H01L51/0097
摘要： Disclosed are semiconductor memory devices containing a plastic substrate and at least one active device supported by the plastic substrate, the active device containing an organic semiconductor material. The semiconductor memory devices containing a plastic substrate may further contain a polymer dielectric and/or a conductive polymer.
摘要翻译：公开了包含塑料基板和由塑料基板支撑的至少一个有源器件的半导体存储器件，该有源器件含有有机半导体材料。包含塑料基板的半导体存储器件还可以包含聚合物电介质和/或导电聚合物。

37. 发明授权

US08035099B2 Diode and resistive memory device structures 有权
标题翻译：二极管和电阻式存储器件结构
公开(公告)号：US08035099B2
公开(公告)日：2011-10-11
申请号：US12072588
申请日：2008-02-27
申请人： Manuj Rathor , An Chen , Steven Avanzino , Suzette K. Pangrle
发明人： Manuj Rathor , An Chen , Steven Avanzino , Suzette K. Pangrle
IPC分类号： H01L29/12
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/24 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/1253
摘要： In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.
摘要翻译：在电子设备中，串联连接二极管和电阻式存储器件。二极管可以采取各种形式，包括氧化物或硅层，并且二极管的一个层可以构成与该二极管串联的电阻存储器件的层。

38. 发明授权

US07776682B1 Ordered porosity to direct memory element formation 有权
标题翻译：有序孔隙直接记忆元素形成
公开(公告)号：US07776682B1
公开(公告)日：2010-08-17
申请号：US11110165
申请日：2005-04-20
申请人： Alexander Nickel , Suzette K. Pangrle , Steven C. Avanzino , Jeffrey Shields , Fei Wang , Minh Tran , Juri H. Krieger , Igor Sokolik
发明人： Alexander Nickel , Suzette K. Pangrle , Steven C. Avanzino , Jeffrey Shields , Fei Wang , Minh Tran , Juri H. Krieger , Igor Sokolik
IPC分类号： H01L21/8242
CPC分类号： H01L45/1233 , H01L27/2472 , H01L45/085 , H01L45/1246 , H01L45/1266 , H01L45/14 , H01L45/141 , H01L45/142 , H01L45/146 , H01L45/149 , H01L45/1616
摘要： Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.
摘要翻译：公开了用于改善记忆单元中电性能的细胞间细胞重复性的方法和系统。所述方法包括在无源层上形成具有有序孔隙率的非导电材料。有序孔隙度可以促进导电通道的形成，电荷载体可以穿过导电通道迁移穿过另外的非导电层以便于改变存储器单元的状态。可以可选地在非导电层上形成阻挡层，并且可以以基本上垂直于导电沟道的方式定向排序的孔隙，使得穿过非导电层迁移的电荷不能渗透到阻挡层。该方法提供了具有成本效益和电可靠性的存储单元的微电子器件的制造。

39. 发明授权

US06977389B2 Planar polymer memory device 有权
标题翻译：平面聚合物记忆装置
公开(公告)号：US06977389B2
公开(公告)日：2005-12-20
申请号：US10452877
申请日：2003-06-02
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Uzodinma Okoroanyanwu , Suzette K. Pangrle
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Uzodinma Okoroanyanwu , Suzette K. Pangrle
IPC分类号： G11C11/56 , G11C13/02 , H01L27/115 , H01L27/24 , H01L27/28 , H01L35/24
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0575
摘要： The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric separate the electrodes. The method for forming a planar polymer memory device comprises at least one of forming a first electrode with an associated plug, forming a second electrode, forming a passive layer over the extension, depositing an organic polymer and patterning the organic polymer. The method affords integration of a planar polymer memory device into a semiconductor fabrication process. A thin film diode (TFD) can further be employed with a planar polymer memory device to facilitate programming. The TFD can be formed between the first electrode and the selectively conductive medium or the second electrode and the selectively conductive medium.
摘要翻译：本发明提供一种能够作为非易失性存储器件操作的平面聚合物存储器件。平面聚合物存储器件可以形成有两个或更多个电极和与一个电极相关联的电极延伸，其中选择性导电的介质和电介质分离电极。用于形成平面聚合物记忆装置的方法包括以下步骤中的至少一种：形成具有相关塞子的第一电极，形成第二电极，在延伸部分上形成钝化层，沉积有机聚合物和图案化有机聚合物。该方法将平面聚合物存储器件集成到半导体制造工艺中。还可以使用薄膜二极管（TFD）与平面聚合物存储器件来促进编程。可以在第一电极和选择性导电介质或第二电极和选择性导电介质之间形成TFD。

40. 发明授权

US06869878B1 Method of forming a selective barrier layer using a sacrificial layer 失效
标题翻译：使用牺牲层形成选择性阻挡层的方法
公开(公告)号：US06869878B1
公开(公告)日：2005-03-22
申请号：US10367406
申请日：2003-02-14
申请人： Ercan Adem , John E. Sanchez , Darrell M. Erb , Suzette K. Pangrle
发明人： Ercan Adem , John E. Sanchez , Darrell M. Erb , Suzette K. Pangrle
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76885
摘要： The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer. The selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket-deposited silicon nitride barrier layer.
摘要翻译：通过用于可靠地沉积对金属化图案有选择性的阻挡层的方法，增强了嵌入在覆盖在半导体晶片衬底上的介电材料层的表面中的电子器件（例如铜）中的平面化金属化图案的可靠性和性能。该方法包括在衬底上形成牺牲介电层。在牺牲电介质层中形成金属化图案。阻挡层选择性地沉积在金属化图案上。通过去除牺牲介电层来去除不期望地沉积在牺牲介电层上的阻挡材料的部分，从而防止相邻金属化特征由阻挡层部分桥接。然后形成层间电介质层代替牺牲电介质层。与常规的覆盖层沉积的氮化硅阻挡层相比，选择性沉积的势垒层有利地减小了金属化特征之间的寄生电容。

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