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1. 发明授权

US09153517B2 Electrical connector between die pad and z-interconnect for stacked die assemblies 有权
标题翻译：用于堆叠模具组件的芯片焊盘和z-互连之间的电连接器
公开(公告)号：US09153517B2
公开(公告)日：2015-10-06
申请号：US13109996
申请日：2011-05-17
申请人： Reynaldo Co , Jeffrey S. Leal , Suzette K. Pangrle , Scott McGrath , DeAnn Eileen Melcher , Keith L. Barrie , Grant Villavicencio , Elmer M. del Rosario , John R. Bray
发明人： Reynaldo Co , Jeffrey S. Leal , Suzette K. Pangrle , Scott McGrath , DeAnn Eileen Melcher , Keith L. Barrie , Grant Villavicencio , Elmer M. del Rosario , John R. Bray
IPC分类号： H01L21/00 , H01L23/31 , H01L25/065 , H01L23/00 , H01L21/683 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/6836 , H01L21/78 , H01L23/3171 , H01L23/3185 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/18 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2224/0235 , H01L2224/02371 , H01L2224/03002 , H01L2224/03318 , H01L2224/0332 , H01L2224/03632 , H01L2224/03848 , H01L2224/05016 , H01L2224/05017 , H01L2224/0529 , H01L2224/05553 , H01L2224/24051 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/94 , H01L2225/06551 , H01L2225/06562 , H01L2225/06568 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2224/03
摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
摘要翻译：在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

2. 发明授权

US09147583B2 Selective die electrical insulation by additive process 有权
标题翻译：通过添加工艺选择性模具电绝缘
公开(公告)号：US09147583B2
公开(公告)日：2015-09-29
申请号：US12913529
申请日：2010-10-27
申请人： Jeffrey S. Leal
发明人： Jeffrey S. Leal
IPC分类号： H01L21/31 , H01L21/469 , H01L21/56 , H01L21/02 , H01L23/00 , H01L25/065
CPC分类号： H01L24/82 , H01L21/02282 , H01L21/02288 , H01L21/31 , H01L21/324 , H01L21/56 , H01L21/76801 , H01L21/76828 , H01L24/19 , H01L24/24 , H01L24/25 , H01L25/0657 , H01L25/50 , H01L2224/19 , H01L2224/24145 , H01L2224/76155 , H01L2224/82051 , H01L2224/82101 , H01L2224/82102 , H01L2224/82355 , H01L2225/06524 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01056 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要： Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
摘要翻译：使用添加剂方法来电绝缘模具堆叠上的选定表面区域; 以及用于在管芯堆叠中电互连管芯的方法包括用于电绝缘管芯的选定表面区域的添加工艺。根据本发明不是绝缘的区域可用于使用以可流动形式施加的导电材料进行电连接以制造导电迹线。

3. 发明授权

US08829677B2 Semiconductor die having fine pitch electrical interconnects 有权
标题翻译：具有细间距电互连的半导体管芯
公开(公告)号：US08829677B2
公开(公告)日：2014-09-09
申请号：US13243877
申请日：2011-09-23
申请人： Keith Lake Barrie , Suzette K. Pangrie , Grant Villavicencio , Jeffrey S. Leal
发明人： Keith Lake Barrie , Suzette K. Pangrie , Grant Villavicencio , Jeffrey S. Leal
IPC分类号： H01L23/28 , H01L23/31 , H01L21/68 , H01L23/00 , H01L25/065 , H01L23/29
CPC分类号： H01L24/83 , H01L23/293 , H01L23/3185 , H01L24/05 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L2224/0345 , H01L2224/0346 , H01L2224/038 , H01L2224/0381 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05567 , H01L2224/05573 , H01L2224/05644 , H01L2224/05664 , H01L2224/1131 , H01L2224/11848 , H01L2224/13017 , H01L2224/1329 , H01L2224/133 , H01L2224/13311 , H01L2224/13313 , H01L2224/13347 , H01L2224/16145 , H01L2224/24051 , H01L2224/24105 , H01L2224/24146 , H01L2224/24226 , H01L2224/244 , H01L2224/245 , H01L2224/24992 , H01L2224/24997 , H01L2224/25175 , H01L2224/2919 , H01L2224/82009 , H01L2224/82039 , H01L2224/82101 , H01L2224/831 , H01L2225/06524 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/12042 , H01L2924/14 , H01L2924/0665 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.
摘要翻译：裸片在互连端附近在互连边缘附近具有互连焊盘，并且互连面的至少一部分由保形电介质涂层覆盖，其中在电介质涂层上的互连迹线与电介质的表面形成高界面角涂层。由于迹线具有较高的界面角度，因此互连材料横向“渗出”的趋势得到缓解，避免了相邻迹线的接触或重叠。互连迹线包括可固化的导电互连材料; 也就是说，它包括可以以可流动形式施加的材料，然后固化或允许其固化以形成导电迹线。此外，一种方法包括在形成迹线之前，用CF 4等离子体处理对保形电介质涂层的表面进行处理。

4. 发明申请

US20110012246A1 Flat Leadless Packages and Stacked Leadless Package Assemblies 有权
标题翻译：扁平无铅封装和堆叠无铅封装组件
公开(公告)号：US20110012246A1
公开(公告)日：2011-01-20
申请号：US12892739
申请日：2010-09-28
申请人： Lawrence Douglas Andrews, JR. , Jeffrey S. Leal , Simon J.S. McElrea
发明人： Lawrence Douglas Andrews, JR. , Jeffrey S. Leal , Simon J.S. McElrea
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/3121 , H01L23/3135 , H01L23/4952 , H01L23/49541 , H01L24/24 , H01L25/105 , H01L2224/24137 , H01L2225/1029 , H01L2225/1064 , H01L2924/14 , H01L2924/00
摘要： A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.
摘要翻译：平坦无引线封装包括至少一个安装在引线框上的管芯，并使用导电聚合物或导电油墨电连接到引线。此外，组件包括使用导电聚合物或导电油墨电连接到引线的堆叠无引线封装。此外，封装模块包括安装在支撑件上并且使用导电聚合物或导电油墨电连接到支撑体中的电路的堆叠的无引线封装的组件。

5. 发明授权

US08912661B2 Stacked die assembly having reduced stress electrical interconnects 有权
标题翻译：堆叠的模具组件具有减小的应力电互连
公开(公告)号：US08912661B2
公开(公告)日：2014-12-16
申请号：US12939524
申请日：2010-11-04
申请人： Scott McGrath , Jeffrey S. Leal , Ravi Shenoy , Loreto Cantillep , Simon McElrea , Suzette K. Pangrle
发明人： Scott McGrath , Jeffrey S. Leal , Ravi Shenoy , Loreto Cantillep , Simon McElrea , Suzette K. Pangrle
IPC分类号： H01L23/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L25/065 , H01L23/498
CPC分类号： H01L21/563 , H01L23/3121 , H01L23/49805 , H01L23/562 , H01L24/06 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/82 , H01L25/0657 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/16225 , H01L2224/24011 , H01L2224/24051 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/73203 , H01L2224/76155 , H01L2224/82102 , H01L2225/06517 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2924/00
摘要： Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.
摘要翻译：公开了用于改进堆叠模具组件中的电互连的方法，并且公开了具有通过该方法形成的结构特征的堆叠模具组件。所得到的堆叠的模具组件的特征在于具有减小的电互连故障。

6. 发明授权

US08159053B2 Flat leadless packages and stacked leadless package assemblies 有权
标题翻译：扁平无引线封装和堆叠无引线封装组件
公开(公告)号：US08159053B2
公开(公告)日：2012-04-17
申请号：US12892739
申请日：2010-09-28
申请人： Lawrence Douglas Andrews, Jr. , Jeffrey S. Leal , Simon J. S. McElrea
发明人： Lawrence Douglas Andrews, Jr. , Jeffrey S. Leal , Simon J. S. McElrea
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/3121 , H01L23/3135 , H01L23/4952 , H01L23/49541 , H01L24/24 , H01L25/105 , H01L2224/24137 , H01L2225/1029 , H01L2225/1064 , H01L2924/14 , H01L2924/00
摘要： A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.
摘要翻译：平坦无引线封装包括至少一个安装在引线框上的管芯，并使用导电聚合物或导电油墨电连接到引线。此外，组件包括使用导电聚合物或导电油墨电连接到引线的堆叠无引线封装。此外，封装模块包括安装在支撑件上并且使用导电聚合物或导电油墨电连接到支撑体中的电路的堆叠的无引线封装的组件。

7. 发明申请

US20120119385A1 Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies 有权
标题翻译：用于堆叠模具组件的模座和Z型互连器之间的电连接器
公开(公告)号：US20120119385A1
公开(公告)日：2012-05-17
申请号：US13109996
申请日：2011-05-17
申请人： Reynaldo Co , Jeffrey S. Leal , Suzette K. Pangrle , Scott McGrath , DeAnn Elleen Melcher , Keith L. Barrie , Grant Villavicencio , Elmer M. del Rosario , John R. Bray
发明人： Reynaldo Co , Jeffrey S. Leal , Suzette K. Pangrle , Scott McGrath , DeAnn Elleen Melcher , Keith L. Barrie , Grant Villavicencio , Elmer M. del Rosario , John R. Bray
IPC分类号： H01L23/52 , H01L21/78
CPC分类号： H01L25/0657 , H01L21/6836 , H01L21/78 , H01L23/3171 , H01L23/3185 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/18 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2224/0235 , H01L2224/02371 , H01L2224/03002 , H01L2224/03318 , H01L2224/0332 , H01L2224/03632 , H01L2224/03848 , H01L2224/05016 , H01L2224/05017 , H01L2224/0529 , H01L2224/05553 , H01L2224/24051 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/94 , H01L2225/06551 , H01L2225/06562 , H01L2225/06568 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2224/03
摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
摘要翻译：在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

8. 发明申请

US20100327461A1 Electrical interconnect for die stacked in zig-zag configuration 有权
标题翻译：用于以锯齿形配置堆叠的管芯的电互连
公开(公告)号：US20100327461A1
公开(公告)日：2010-12-30
申请号：US12821454
申请日：2010-06-23
申请人： Reynaldo Co , Grant Villavicencio , Jeffrey S. Leal , Simon J.S. McElrea
发明人： Reynaldo Co , Grant Villavicencio , Jeffrey S. Leal , Simon J.S. McElrea
IPC分类号： H01L25/065 , H01L21/60 , H01L21/77 , H01L23/538
CPC分类号： H01L25/0657 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/76155 , H01L2224/82102 , H01L2224/92244 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/14
摘要： A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support. Die in the first tier are electrically interconnected die-to-die, and the tier is electrically connected to a support, by traces of an electrically conductive material contacting interconnect pads on the die and a first set of bond pads on the support. Pillars of a electrically conductive material are formed on a second set of bond pads, and die in the second tier are electrically interconnected die-to-die, and the tier is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the substrate.
摘要翻译：模具（或一堆模具）安装在支撑件上并在支撑件上方升高，并且电连接到支撑件中的电路。导电材料的支柱形成在支撑件的安装侧的一组接合焊盘上，并且升高的模具（或模具的升高堆叠中的至少一个模具）通过电气迹线电连接到支撑件导电材料将管芯上的互连焊盘接触到支柱，并且通过支柱到支撑件。而且，以Z字形配置的分层偏移堆叠模组组件，其中第一（下）层的第一方向上的互连边缘和第二层（第二层）堆叠在第一层上的互连边缘，在与第一方向不同的第二方向上面对电连接到支撑件。在第一层中的管芯被电连接到芯片之间，并且该层通过导电材料的痕迹电连接到支撑件，导电材料接触管芯上的互连焊盘和支撑件上的第一组接合焊盘。导电材料的支柱形成在第二组接合焊盘上，并且第二层中的管芯与管芯电连接，并且该层通过迹线导电材料接触互连模具上的垫子到柱子上，并通过柱子到基底。

9. 发明申请

US20100140811A1 SEMICONDUCTOR DIE INTERCONNECT FORMED BY AEROSOL APPLICATION OF ELECTRICALLY CONDUCTIVE MATERIAL 审中-公开
标题翻译：气溶胶应用电导体材料形成的半导体DIE互连
公开(公告)号：US20100140811A1
公开(公告)日：2010-06-10
申请号：US12634598
申请日：2009-12-09
申请人： Jeffrey S. Leal , Scott McGrath , Suzette K. Pangrle
发明人： Jeffrey S. Leal , Scott McGrath , Suzette K. Pangrle
IPC分类号： H01L23/52 , H01L21/50
CPC分类号： H01L24/76 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/24051 , H01L2224/24145 , H01L2224/24146 , H01L2224/24226 , H01L2224/24998 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/76155 , H01L2224/82007 , H01L2224/82102 , H01L2225/06551 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet.
摘要翻译：通过以气溶胶形式施加导电材料，例如通过气溶胶喷射印刷，在半导体管芯上形成互连端子。而且，通过施加与气泡形式的导电材料，与模具上的焊盘或模具上的焊盘接触，形成堆叠裸片之间或芯片之间的电互连，以及下层支撑件（例如封装衬底）中的电路之间的电互连基板，并在相应的焊盘之间通过。在一些实施例中，在由模具的互连侧壁形成的内角处形成圆角，并且在底层特征（下面的模具或支撑件）上的垫的表面内侧形成圆角; 并且导电材料经过圆角的表面。

10. 发明申请

US20090206458A1 FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES 失效
标题翻译：平面无铅封装和堆叠无铅封装组件
公开(公告)号：US20090206458A1
公开(公告)日：2009-08-20
申请号：US12199667
申请日：2008-08-27
申请人： LAWRENCE DOUGLAS ANDREWS, JR. , JEFFREY S. LEAL , SIMON J.S. McELREA
发明人： LAWRENCE DOUGLAS ANDREWS, JR. , JEFFREY S. LEAL , SIMON J.S. McELREA
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/3121 , H01L23/3135 , H01L23/4952 , H01L23/49541 , H01L24/24 , H01L25/105 , H01L2224/24137 , H01L2225/1029 , H01L2225/1064 , H01L2924/14 , H01L2924/00
摘要： A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.
摘要翻译：平坦无引线封装包括至少一个安装在引线框上的管芯，并使用导电聚合物或导电油墨电连接到引线。此外，组件包括使用导电聚合物或导电油墨电连接到引线的堆叠无引线封装。此外，封装模块包括安装在支撑件上并且使用导电聚合物或导电油墨电连接到支撑体中的电路的堆叠的无引线封装的组件。

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