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31. 发明申请

US20050048778A1 Use of thin SOI to inhibit relaxation of SiGe layers 有权
标题翻译：使用薄SOI抑制SiGe层的弛豫
公开(公告)号：US20050048778A1
公开(公告)日：2005-03-03
申请号：US10654232
申请日：2003-09-03
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： H01L29/161 , C30B29/52 , C30B31/02 , H01L21/02 , H01L21/20 , H01L21/205 , H01L21/762 , H01L21/8238 , H01L27/12 , H01L29/04 , C30B1/00 , C30B3/00 , C30B5/00 , C30B28/02 , H01L21/302 , H01L21/461
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
摘要翻译：在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化温度。因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

32. 发明授权

US06177289B1 Lateral trench optical detectors 失效
标题翻译：横向沟槽光学检测器
公开(公告)号：US06177289B1
公开(公告)日：2001-01-23
申请号：US09205433
申请日：1998-12-04
申请人： John Crow , Steve Koester , Daniel M. Kuchta , Dennis L. Rogers , Devendra Sadana , Sandip Tiwari
发明人： John Crow , Steve Koester , Daniel M. Kuchta , Dennis L. Rogers , Devendra Sadana , Sandip Tiwari
IPC分类号： H01L2166
CPC分类号： H01L31/03529 , H01L31/035281 , H01L31/105 , Y02E10/50
摘要： A monolithic semiconductor optical detector is formed on a substrate having a plurality of substantially parallel trenches etched therein. The trenches are further formed as a plurality of alternating N-type and P-type trench regions separated by pillar regions of the substrate which operate as an I region between the N and P trench regions. First and second contacts are formed on the surface of the substrate and interconnect the N-type trench regions and the P-type trench regions, respectively. Preferably, the trenches are etched with a depth comparable to an optical extinction length of optical radiation to which the detector is responsive.
摘要翻译：单片半导体光检测器形成在其上蚀刻有多个基本上平行的沟槽的衬底上。沟槽还形成为由作为N沟道区域和P沟道区域之间的I区域的基板的柱状区域分离的多个交替的N型和P型沟槽区域。第一和第二触点形成在衬底的表面上并分别互连N型沟槽区和P型沟槽区。优选地，以与检测器响应的光辐射的光消光长度相当的深度蚀刻沟槽。

33. 发明申请

US20080116483A1 HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT 失效
标题翻译：高品质SGOI通过靠近合金熔点来退火
公开(公告)号：US20080116483A1
公开(公告)日：2008-05-22
申请号：US12027561
申请日：2008-02-07
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
IPC分类号： H01L29/165
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓形成堆垛层错缺陷。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

34. 发明申请

US20080057684A1 METHOD FOR FABRICATING LOW-DEFECT-DENSITY CHANGED ORIENTATION Si 失效
标题翻译：用于制造低密度变化方位的方法Si
公开(公告)号：US20080057684A1
公开(公告)日：2008-03-06
申请号：US11873928
申请日：2007-10-17
申请人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
发明人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/2022
摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.
摘要翻译：本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向具有不同的方向。更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶非晶层的原始方向。本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

35. 发明申请

US20070257315A1 Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors 审中-公开
标题翻译：离子注入与原位或非原位热处理相结合，用于改进的场效应晶体管
公开(公告)号：US20070257315A1
公开(公告)日：2007-11-08
申请号：US11417846
申请日：2006-05-04
申请人： Stephen Bedell , Joel De Souza , Zhibin Ren , Alexander Reznicek , Devendra Sadana , Katherine Saenger , Ghavam Shahidi
发明人： Stephen Bedell , Joel De Souza , Zhibin Ren , Alexander Reznicek , Devendra Sadana , Katherine Saenger , Ghavam Shahidi
IPC分类号： H01L21/8234
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/324 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78684 , Y10S438/909 , Y10S438/943
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
摘要翻译：本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法，以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

36. 发明申请

US20060154442A1 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide 有权
标题翻译：使用亲水硅表面的准疏水Si-Si晶片结合和界面结合氧化物的溶解
公开(公告)号：US20060154442A1
公开(公告)日：2006-07-13
申请号：US11031165
申请日：2005-01-07
申请人： Joel de Souza , John Ott , Alexander Reznicek , Devendra Sadana , Katherine Saenger
发明人： Joel de Souza , John Ott , Alexander Reznicek , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/46
CPC分类号： H01L21/187 , H01L21/76251
摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.
摘要翻译：本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与通过疏水性接合实现的性能相当的特性的结合Si-Si界面的方法。约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

37. 发明申请

US20060057403A1 Use of thin SOI to inhibit relaxation of SiGe layers 审中-公开
公开(公告)号：US20060057403A1
公开(公告)日：2006-03-16
申请号：US11268096
申请日：2005-11-07
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： B32B13/04 , B32B15/04 , B32B9/00
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

38. 发明申请

US20060042542A1 Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers 有权
公开(公告)号：US20060042542A1
公开(公告)日：2006-03-02
申请号：US10932598
申请日：2004-09-02
申请人： Stephen Bedell , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Keith Fogel , Devendra Sadana
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： H01L21/76254
摘要： A method of fabricating a high-quality relaxed SiGe-on-insulator substrate material is provided in which a prefabricated silicon-on-insulator substrate is first exposed to an unstrained Ge-containing source and then heated (annealed/oxidized) to cause Ge diffusion and thermal mixing of Ge within a single-crystal Si-containing layer of the prefabricated silicon-on-insulator substrate. The unstrained Ge-containing source can comprise a solid Ge-containing source, a gaseous Ge-containing source, or ions of Ge.

39. 发明申请

US20050208780A1 High-quality SGOI by oxidation near the alloy melting temperature 有权
标题翻译：高品质的SGOI通过氧化在合金熔化温度附近
公开(公告)号：US20050208780A1
公开(公告)日：2005-09-22
申请号：US11029921
申请日：2005-01-05
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： C30B1/00 , H01L21/00 , H01L21/20 , H01L21/324 , H01L21/477 , H01L21/762 , H01L27/01
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。

40. 发明申请

US20050148161A1 Method of preventing surface roughening during hydrogen prebake of SiGe substrates 失效
公开(公告)号：US20050148161A1
公开(公告)日：2005-07-07
申请号：US10751208
申请日：2004-01-02
申请人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephan Bedell , Devendra Sadana
发明人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephan Bedell , Devendra Sadana
IPC分类号： C30B25/02 , C30B29/06 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/28 , H01L21/306 , H01L21/3205 , H01L21/36 , H01L21/44
CPC分类号： H01L21/02046 , C30B25/02 , C30B29/06 , C30B29/52 , H01L21/02052 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/02661 , Y10S438/933
摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013-1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process which heats the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface sufficiently to remove additional oxygen from the surface and leave a second amount of oxygen, less than the first amount, on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The heating process leaves an amount of at least 5×1012/cm2 of oxygen (typically, between approximately 1×1013/cm2 and approximately 5×1013/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. By leaving a small amount of oxygen on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

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