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31. 发明授权

US06864180B2 Method for reworking low-k polymers used in semiconductor structures 失效
标题翻译：用于半导体结构中使用的低k聚合物的再加工方法
公开(公告)号：US06864180B2
公开(公告)日：2005-03-08
申请号：US09969363
申请日：2001-10-02
申请人： Darryl D. Restaino , Delores Bennett , John A. Fitzsimmons , John Fritche , Jeffrey C. Hedrick , Chih-Chien Liu , Shahab Siddiqui , Christy S. Tyberg
发明人： Darryl D. Restaino , Delores Bennett , John A. Fitzsimmons , John Fritche , Jeffrey C. Hedrick , Chih-Chien Liu , Shahab Siddiqui , Christy S. Tyberg
IPC分类号： H01L21/311
CPC分类号： H01L21/31138 , H01L21/31111
摘要： A method for removing a dielectric layer formed upon a semiconductor substrate is disclosed. In an exemplary embodiment of the invention, the method includes subjecting the dielectric layer to a dry etch process and subjecting an adhesion promoter layer underneath the dielectric layer to a wet etch process.
摘要翻译：公开了一种去除在半导体衬底上形成的电介质层的方法。在本发明的示例性实施例中，该方法包括对介电层进行干蚀刻工艺，并对介电层下面的粘附促进剂层进行湿蚀刻工艺。

32. 发明授权

US07888741B2 Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same 有权
标题翻译：具有改善SiCOH电介质界面强度的结构及其制备方法
公开(公告)号：US07888741B2
公开(公告)日：2011-02-15
申请号：US11406595
申请日：2006-04-19
申请人： Daniel C. Edelstein , Alfred Grill , Vishnubhai V. Patel , Darryl D. Restaino
发明人： Daniel C. Edelstein , Alfred Grill , Vishnubhai V. Patel , Darryl D. Restaino
IPC分类号： H01L29/12
CPC分类号： H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02274 , H01L21/02315 , H01L21/3122 , H01L21/31633 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.
摘要翻译：半导体器件结构和制造方法包括具有顶部第一层的衬底; 位于所述第一层顶部的第二薄过渡层; 以及位于所述过渡层顶部的第三层，其中所述第二薄过渡层在所述结构的所述第一和第三层之间提供强粘合力和内聚强度。此外，半导体器件结构和制造方法包括绝缘结构，其包括多个介电层和导电层，其中设置有各自的过渡键合层以增强不同层之间的界面强度。此外，电子器件结构包括绝缘和导电材料层，作为后端线（“BEOL”）布线结构中的层间或层间电介质，其中不同对的介电膜之间的界面强度由薄的中间过渡粘合层。

33. 发明授权

US07847402B2 BEOL interconnect structures with improved resistance to stress 有权
标题翻译： BEOL互连结构具有改善的抗应力
公开(公告)号：US07847402B2
公开(公告)日：2010-12-07
申请号：US11676522
申请日：2007-02-20
申请人： Darryl D. Restaino , Griselda Bonilla , Christos D. Dimitrakopoulos , Stephen M. Gates , Jae H. Kim , Michael W. Lane , Xiao H. Liu , Son V. Nguyen , Thomas M. Shaw , Johnny Widodo
发明人： Darryl D. Restaino , Griselda Bonilla , Christos D. Dimitrakopoulos , Stephen M. Gates , Jae H. Kim , Michael W. Lane , Xiao H. Liu , Son V. Nguyen , Thomas M. Shaw , Johnny Widodo
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/53295 , H01L21/76822 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.
摘要翻译：提供了包括后端行（“BEOL”）互连结构的芯片。 BEOL互连结构包括多个层间电介质（“ILD”）层，其包括通过紫外线（“UV”）辐射固化的电介质材料。多个金属互连配线层嵌入在多个ILD层中。介电阻挡层覆盖多个金属互连布线层，介电阻挡层适于减少材料在金属互连布线层和ILD层之间的扩散。介质阻挡层中的一个适于保持压缩应力，同时承受足以固化ILD层的介电材料的UV辐射，使得BEOL结构更好地能够避免由于热和/或机械应力引起的变形。

34. 发明授权

US07737029B2 Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby 有权
标题翻译：使用除氧等离子体和由此形成的互连结构在半导体衬底上形成金属互连结构的方法
公开(公告)号：US07737029B2
公开(公告)日：2010-06-15
申请号：US12050354
申请日：2008-03-18
申请人： Jae-hak Kim , Griselda Bonilla , Steven E. Molis , Darryl D. Restaino , Hosadurga Shobha , Johnny Widodo
发明人： Jae-hak Kim , Griselda Bonilla , Steven E. Molis , Darryl D. Restaino , Hosadurga Shobha , Johnny Widodo
IPC分类号： H01L21/321
CPC分类号： H01L23/53233 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76876 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 Å to about 50 Å and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.
摘要翻译：形成器件的方法包括在衬底上形成其中具有金属互连的第一电绝缘层，然后在金属互连的上表面上和第一电绝缘层上形成第一电绝缘阻挡层。第一电绝缘阻挡层暴露于穿过第一电绝缘屏障并从金属互连的上表面除去氧的等离子体。阻挡层的厚度可以在约5至约埃的范围内，等离子体可以是将金属互连的上表面上的氧转化为水的含氢等离子体。

35. 发明申请

US20090181544A1 METHOD FOR PREVENTING BACKSIDE DEFECTS IN DIELECTRIC LAYERS FORMED ON SEMICONDUCTOR SUBSTRATES 有权
标题翻译：用于防止在半导体衬底上形成的电介质层中的背面缺陷的方法
公开(公告)号：US20090181544A1
公开(公告)日：2009-07-16
申请号：US11972895
申请日：2008-01-11
申请人： Chester T. Dziobkowski , Thomas F. Houghton , Emily Kinser , Darryl D. Restaino , Yun-Yu Wang
发明人： Chester T. Dziobkowski , Thomas F. Houghton , Emily Kinser , Darryl D. Restaino , Yun-Yu Wang
IPC分类号： H01L21/311
CPC分类号： H01L21/31612 , C23C16/325 , C23C16/505 , C23C16/56 , H01L21/02131 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/3145 , H01L21/3148 , H01L21/31629
摘要： A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.
摘要翻译：在形成在衬底上的氮掺杂碳化硅或氮掺杂氢化碳化硅层上形成TEOS氧化物层的方法。该方法包括在靠近衬底顶表面的顶表面和顶侧倾斜边缘上形成氮掺杂碳化硅或氮掺杂氢化碳化硅层; 去除或阻止在靠近基底的底表面的底侧斜边缘区域上形成富碳层，或将富碳层转化为氮掺杂碳化硅或氮掺杂氢化碳化硅; 以及在所述基板的顶面，顶侧倾斜边缘和底侧斜边缘区域上形成TEOS氧化物层。

36. 发明申请

US20080197513A1 BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS 有权
标题翻译： BEOL互连结构具有改善的抗应力
公开(公告)号：US20080197513A1
公开(公告)日：2008-08-21
申请号：US11676522
申请日：2007-02-20
申请人： Darryl D. Restaino , Griselda Bonilla , Christos D. Dimitrakopoulos , Stephen M. Gates , Jae H. Kim , Michael W. Lane , Xiao H. Liu , Son V. Nguyen , Thomas M. Shaw , Johnny Widodo
发明人： Darryl D. Restaino , Griselda Bonilla , Christos D. Dimitrakopoulos , Stephen M. Gates , Jae H. Kim , Michael W. Lane , Xiao H. Liu , Son V. Nguyen , Thomas M. Shaw , Johnny Widodo
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/53295 , H01L21/76822 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.
摘要翻译：提供了包括后端行（“BEOL”）互连结构的芯片。 BEOL互连结构包括多个层间电介质（“ILD”）层，其包括通过紫外线（“UV”）辐射固化的电介质材料。多个金属互连配线层嵌入在多个ILD层中。介电阻挡层覆盖多个金属互连布线层，介电阻挡层适于减少材料在金属互连布线层和ILD层之间的扩散。介质阻挡层中的一个适于保持压缩应力，同时承受足以固化ILD层的介电材料的UV辐射，使得BEOL结构更好地能够避免由于热和/或机械应力引起的变形。

37. 发明申请

US20080057697A1 Methods of Forming Dual-Damascene Interconnect Structures Using Adhesion Layers Having High Internal Compressive Stress and Structures Formed Thereby 有权
标题翻译：使用具有高内压应力和结构的粘结层形成双镶嵌互连结构的方法
公开(公告)号：US20080057697A1
公开(公告)日：2008-03-06
申请号：US11470320
申请日：2006-09-06
申请人： Jaehak Kim , Darryl D. Restaino , Johnny Widodo
发明人： Jaehak Kim , Darryl D. Restaino , Johnny Widodo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/02164 , H01L21/02271 , H01L21/31608 , H01L21/31633 , H01L21/76807 , H01L21/76832
摘要： Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 to about 3000 sccm. The goal of the deposition step is to achieve an adhesion layer having an internal compressive stress of greater than about 150 MPa therein, so that the adhesion layer is less susceptible to etching/cleaning damage and moisture absorption during back-end processing steps. Additional dielectric and metal layers are then deposited on the adhesion layer.
摘要翻译：形成互连结构的方法包括在第一介电层上形成第一金属布线图案，并在第一铜布线图案上形成覆盖层（例如SiCN层）。使用包含八甲基环四硅烷（OMCTS）的第一源气体以约500sccm至约700sccm范围内的体积流速和第二气体以一定范围内的体积流量沉积粘合层，约1000至约3000sccm。沉积步骤的目的是实现其中具有大于约150MPa的内部压缩应力的粘合层，使得粘附层在后端加工步骤期间较不易于蚀刻/清洁损伤和吸湿。然后在附着层上沉积附加的电介质层和金属层。

38. 发明授权

US06493078B1 Method and apparatus to improve coating quality 有权
标题翻译：提高涂料质量的方法和设备
公开(公告)号：US06493078B1
公开(公告)日：2002-12-10
申请号：US09956367
申请日：2001-09-19
申请人： John A. Fitzsimmons , Darryl D. Restaino , Michael J. Schade
发明人： John A. Fitzsimmons , Darryl D. Restaino , Michael J. Schade
IPC分类号： G01N2100
CPC分类号： G01N21/9501 , G01N21/9503 , G01N2021/8427
摘要： A method and structure for improving a coating on a substrate comprises a chamber further comprising a rotatable holder, which holds the substrate; a supply of coating material for coating the substrate in the chamber; a window in the wall of the chamber; and a supply of liquid for coating at least a portion of the window on the interior side of the chamber. The chamber is preferably adapted to house the window in multiple configurations. A camera (or other optical detector), which is positioned outside of the chamber, monitors the substrate through the window.
摘要翻译：用于改善衬底上的涂层的方法和结构包括：腔室，其还包括保持衬底的可旋转保持器; 供应用于在所述室中涂覆所述基材的涂料; 在房间的墙壁上的一个窗口; 以及用于在室的内侧涂覆窗口的至少一部分的液体供应。该室优选适于将窗户容纳在多种构型中。位于室外的相机（或其他光学检测器）通过窗口监测基板。

39. 发明授权

US06176931B1 Wafer clamp ring for use in an ionized physical vapor deposition apparatus 失效
标题翻译：用于电离物理气相沉积设备的晶片夹环
公开(公告)号：US06176931B1
公开(公告)日：2001-01-23
申请号：US09430829
申请日：1999-10-29
申请人： Darryl D. Restaino , Stephen Mark Rossnagel , Andrew Herbert Simon , Pavel Smetana , Edward C. Cooney, III
发明人： Darryl D. Restaino , Stephen Mark Rossnagel , Andrew Herbert Simon , Pavel Smetana , Edward C. Cooney, III
IPC分类号： C23C1600
CPC分类号： C23C14/541 , C23C14/50
摘要： Improvements are described for a wafer clamp ring used in an IPVD apparatus to provide cooling for the wafer clamp ring, to protect the wafer clamp ring from ion bombardment, and to prevent damage to the wafer. The wafer clamp ring is placed on a cooling fixture when not required for a deposition process. The fixture is annular in shape and in close thermal contact with a circulating coolant and is thereby cooled below ambient temperature. The cooling line and the cooling fixture are fixed relative to the IPVD device, so that problems associated with flexible cooling lines are avoided. An annular grounded shield may be provided between the plasma and clamp ring to protect the clamp ring against ion bombardment during the deposition process. The wafer clamp ring may have a portion which overhangs the wafer during a deposition process, and which has a ridge portion extending downwards therefrom and tapering to a knife edge. The wafer clamp ring may be fabricated as a split ring with an insulating portion, to prevent heating by induced current in the clamp ring.
摘要翻译：描述了用于IPVD装置中的晶片夹环的改进，以为晶片夹环提供冷却，以保护晶片夹环避免离子轰击，并防止损坏晶片。当不需要沉积工艺时，将晶片夹环放置在冷却夹具上。固定装置的形状为环形，与循环的冷却剂紧密的热接触，从而被冷却到环境温度以下。冷却管路和冷却固定装置相对于IPVD装置固定，从而避免与柔性冷却管线相关的问题。可以在等离子体和夹环之间设置环形接地屏蔽件，以在沉积过程中保护夹环免受离子轰击。晶片夹环可以具有在沉积工艺期间悬垂于晶片的部分，并且具有从其向下延伸并逐渐变细到刀刃的脊部分。晶片夹环可以制造成具有绝缘部分的开口环，以防止夹紧环中的感应电流加热。

40. 发明授权

US6159870A Borophosphosilicate glass incorporated with fluorine for low thermal budget gap fill 失效
标题翻译：掺有氟的硼磷硅玻璃用于低热量预算缺口填充
公开(公告)号：US6159870A
公开(公告)日：2000-12-12
申请号：US210411
申请日：1998-12-11
申请人： Ashima B. Chakravarti , Richard A. Conti , Frank V. Liucci , Darryl D. Restaino
发明人： Ashima B. Chakravarti , Richard A. Conti , Frank V. Liucci , Darryl D. Restaino
IPC分类号： H01L21/20 , H01L21/316 , H01L21/31 , H01L21/469
CPC分类号： H01L21/31604 , H01L21/31625 , H01L21/31629
摘要： A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750.degree. C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.1 to 2.0 wt % fluorine.
摘要翻译：在半导体器件上沉积氟化硼磷硅酸盐玻璃（FBPSG）作为最终或层间绝缘膜的方法。纵横比大于6:1的间隙在约200托的亚大气压下，在约480℃的温度下填充基本上无空隙的FBPSG膜。优选地，在该方法中使用的气态反应物包括具有臭氧/氧混合物的TEOS，FTES，TEPO和TEB。硼和磷的掺杂浓度足够低，从而避免表面微晶缺陷和吸湿性。较低纵横比间隙的沉积膜基本上无空隙，使得不需要膜的后续退火。沉积在较高纵横比间隙中的膜在大约750℃或更低温度下退火，完全在大多数DRAM，逻辑和合并逻辑DRAM芯片的热预算内。所得的FBPSG层含有小于或等于约5.0重量％的硼，小于约4.0重量％的磷和约0.1至2.0重量％的氟。

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