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1. 发明申请

US20090181544A1 METHOD FOR PREVENTING BACKSIDE DEFECTS IN DIELECTRIC LAYERS FORMED ON SEMICONDUCTOR SUBSTRATES 有权
标题翻译：用于防止在半导体衬底上形成的电介质层中的背面缺陷的方法
公开(公告)号：US20090181544A1
公开(公告)日：2009-07-16
申请号：US11972895
申请日：2008-01-11
申请人： Chester T. Dziobkowski , Thomas F. Houghton , Emily Kinser , Darryl D. Restaino , Yun-Yu Wang
发明人： Chester T. Dziobkowski , Thomas F. Houghton , Emily Kinser , Darryl D. Restaino , Yun-Yu Wang
IPC分类号： H01L21/311
CPC分类号： H01L21/31612 , C23C16/325 , C23C16/505 , C23C16/56 , H01L21/02131 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/3145 , H01L21/3148 , H01L21/31629
摘要： A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.
摘要翻译：在形成在衬底上的氮掺杂碳化硅或氮掺杂氢化碳化硅层上形成TEOS氧化物层的方法。该方法包括在靠近衬底顶表面的顶表面和顶侧倾斜边缘上形成氮掺杂碳化硅或氮掺杂氢化碳化硅层; 去除或阻止在靠近基底的底表面的底侧斜边缘区域上形成富碳层，或将富碳层转化为氮掺杂碳化硅或氮掺杂氢化碳化硅; 以及在所述基板的顶面，顶侧倾斜边缘和底侧斜边缘区域上形成TEOS氧化物层。

2. 发明授权

US07910484B2 Method for preventing backside defects in dielectric layers formed on semiconductor substrates 有权
标题翻译：防止在半导体基板上形成的电介质层的背面缺陷的方法
公开(公告)号：US07910484B2
公开(公告)日：2011-03-22
申请号：US11972895
申请日：2008-01-11
申请人： Chester T. Dziobkowski , Thomas F. Houghton , Emily Kinser , Darryl D. Restaino , Yun-Yu Wang
发明人： Chester T. Dziobkowski , Thomas F. Houghton , Emily Kinser , Darryl D. Restaino , Yun-Yu Wang
IPC分类号： H01L21/302 , H01L21/461 , H01L21/311
CPC分类号： H01L21/31612 , C23C16/325 , C23C16/505 , C23C16/56 , H01L21/02131 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/3145 , H01L21/3148 , H01L21/31629
摘要： A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.
摘要翻译：在形成在衬底上的氮掺杂碳化硅或氮掺杂氢化碳化硅层上形成TEOS氧化物层的方法。该方法包括在靠近衬底顶表面的顶表面和顶侧倾斜边缘上形成氮掺杂碳化硅或氮掺杂氢化碳化硅层; 去除或防止在靠近衬底的底表面的底侧斜边缘区域上形成富碳层，或将富碳层转化为氮掺杂碳化硅或氮掺杂氢化碳化硅; 以及在所述基板的顶面，顶侧倾斜边缘和底侧斜边缘区域上形成TEOS氧化物层。

3. 发明授权

US07179760B2 Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making same 失效
标题翻译：双层盖结构，包括用于导电金属化的HDP / bHDP膜及其制造方法
公开(公告)号：US07179760B2
公开(公告)日：2007-02-20
申请号：US10908833
申请日：2005-05-27
申请人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.
摘要翻译：本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层）选择性。

4. 发明授权

US4721689A Method for simultaneously forming an interconnection level and via studs 失效
标题翻译：同时形成互连级别和通孔柱的方法
公开(公告)号：US4721689A
公开(公告)日：1988-01-26
申请号：US901492
申请日：1986-08-28
申请人： Paul N. Chaloux, Jr. , Thomas F. Houghton , Richard K. West
发明人： Paul N. Chaloux, Jr. , Thomas F. Houghton , Richard K. West
IPC分类号： H01L23/522 , H01L21/768 , C23F1/02 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76877
摘要： A method for simultaneously forming a level of interconnection metallurgy over, and inter-level via studs through, an insulating layer of a semiconductor chip. The method comprises the steps of forming a plurality of via holes in the insulating layer, high-mobility sputtering conductive material on to the surface of the insulating layer and into the via holes therein, masking the conductive material layer, and then ion beam milling through the mask to form a patterned interconnection layer. The high-mobility sputtering step is accomplished by reducing the background pressure to below 10.sup.-7 Torr to eliminate non-mobile species, maintaining a sputter pressure of less than 7 microns, maintaining an appropriate chip bias level to keep the conductive material molecules mobile until they reach their lowest energy state, and maintaining the temperature of the chip at a level so that a high sputter species mobility is maintained. This high-mobility sputtering forms a substantially planar conductive layer and fills the via holes without void formation. The foregoing process permits extremely dense interconnection levels, is especially suited for multiple interconnection level designs, and is extendable to large diameter wafer fabrication.
摘要翻译：一种用于通过半导体芯片的绝缘层同时形成互连冶金级别和级间通孔柱的方法。该方法包括以下步骤：在绝缘层中形成多个通孔，将高迁移率溅射导电材料放置在绝缘层的表面上并进入其中的通孔中，掩蔽导电材料层，然后离子束研磨通过该掩模形成图案化的互连层。高迁移率溅射步骤是通过将背景压力降低到低于10-7乇来实现的，以消除非移动物质，保持小于7微米的溅射压力，保持适当的芯片偏置水平以保持导电材料分子移动直到它们达到其最低能量状态，并将芯片的温度保持在一个水平，从而保持高的溅射物质迁移率。该高迁移率溅射形成基本上平面的导电层，并填充通孔而无空隙形成。上述过程允许非常密集的互连级别，特别适用于多个互连级别设计，并且可扩展到大直径晶片制造。

5. 发明授权

US08613996B2 Polymeric edge seal for bonded substrates 有权
标题翻译：粘合基材的聚合物边缘密封
公开(公告)号：US08613996B2
公开(公告)日：2013-12-24
申请号：US12603002
申请日：2009-10-21
申请人： Mukta G. Farooq , Thomas F. Houghton , Nitin Parbhoo , Richard P. Volant
发明人： Mukta G. Farooq , Thomas F. Houghton , Nitin Parbhoo , Richard P. Volant
IPC分类号： B32B7/00
CPC分类号： B32B37/1292 , B32B3/02 , B32B27/08 , B32B37/1284 , B32B2457/14 , H01L21/187 , Y10T156/10 , Y10T156/1064 , Y10T428/215 , Y10T428/219 , Y10T428/24355 , Y10T428/24752 , Y10T428/24777 , Y10T428/24802 , Y10T428/24851
摘要： A layer of polymer material is applied on a peripheral region of at least one of the two substrates to be bonded prior to bonding. The bonded structure formed thereby includes a first substrate, a second substrate in direct contact with the first substrate, and a ring of the polymer material in direct contact with the first substrate at a first interface and in direct contact with the second substrate. The ring of polymer material laterally surrounds and seals the interface at which the first substrate contacts the second substrate. A ring-shaped cavity can be formed within the polymeric ring. Alternately, the first interface and the second interface can be contiguous without a ring-shaped cavity between the first and second substrates.
摘要翻译：在接合之前，将待结合的两个基板中的至少一个的外围区域上施加一层聚合物材料。由此形成的接合结构包括第一基板，与第一基板直接接触的第二基板，以及在第一界面处与第一基板直接接触并与第二基板直接接触的聚合物材料的环。聚合物材料环横向包围并密封第一基底与第二基底接触的界面。可以在聚合物环内形成环形空腔。或者，第一界面和第二界面可以相邻，而在第一和第二基板之间没有环形腔。

6. 发明申请

US20110091685A1 POLYMERIC EDGE SEAL FOR BONDED SUBSTRATES 有权
标题翻译：用于粘合基材的聚合物边缘密封
公开(公告)号：US20110091685A1
公开(公告)日：2011-04-21
申请号：US12603002
申请日：2009-10-21
申请人： Mukta G. Farooq , Thomas F. Houghton , Nitin Parbhoo , Richard P. Volant
发明人： Mukta G. Farooq , Thomas F. Houghton , Nitin Parbhoo , Richard P. Volant
IPC分类号： B32B7/00 , B32B37/00
CPC分类号： B32B37/1292 , B32B3/02 , B32B27/08 , B32B37/1284 , B32B2457/14 , H01L21/187 , Y10T156/10 , Y10T156/1064 , Y10T428/215 , Y10T428/219 , Y10T428/24355 , Y10T428/24752 , Y10T428/24777 , Y10T428/24802 , Y10T428/24851
摘要： A layer of polymer material is applied on a peripheral region of at least one of the two substrates to be bonded prior to bonding. The bonded structure formed thereby includes a first substrate, a second substrate in direct contact with the first substrate, and a ring of the polymer material in direct contact with the first substrate at a first interface and in direct contact with the second substrate. The ring of polymer material laterally surrounds and seals the interface at which the first substrate contacts the second substrate. A ring-shaped cavity can be formed within the polymeric ring. Alternately, the first interface and the second interface can be contiguous without a ring-shaped cavity between the first and second substrates.
摘要翻译：在接合之前，将待结合的两个基板中的至少一个的外围区域上施加一层聚合物材料。由此形成的接合结构包括第一基板，与第一基板直接接触的第二基板，以及在第一界面处与第一基板直接接触并与第二基板直接接触的聚合物材料的环。聚合物材料环横向包围并密封第一基底与第二基底接触的界面。可以在聚合物环内形成环形空腔。或者，第一界面和第二界面可以相邻，而在第一和第二基板之间没有环形腔。

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