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31. 发明申请

US20080117702A1 INTEGRATED CIRCUIT HAVING A MEMORY WITH PROCESS-VOLTAGE-TEMPERATURE CONTROL 有权
标题翻译：具有过程电压控制的存储器的集成电路
公开(公告)号：US20080117702A1
公开(公告)日：2008-05-22
申请号：US11860891
申请日：2007-09-25
申请人： Matthew R. Henry , Douglas D. Lopata , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Matthew R. Henry , Douglas D. Lopata , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： G11C7/04 , G11C7/02
CPC分类号： G11C7/04 , G11C7/22 , G11C2207/104
摘要： Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.
摘要翻译：本发明的某些实施例提供一种集成电路（IC），其具有可操作地耦合到PVT（过程电压 - 温度）源和可调节存储器的处理器。处理器从源头接收表征当前PVT条件的输入，并且基于该输入生成用于存储器的命令。响应于该命令，存储器调整其内部电路结构，时钟速度和/或工作电压以优化其对于当前PVT条件的性能。有利地，调整存储器以使其能够维持其功能并在不利的PVT条件下提供可接受的性能水平的能力在选择电路设计选项方面提供了额外的灵活性，其可以产生区域节省和/或增加可接受的IC的产量制造。

32. 发明申请

US20110157964A1 Memory Cell Using Leakage Current Storage Mechanism 审中-公开
标题翻译：使用泄漏电流存储机制的存储单元
公开(公告)号：US20110157964A1
公开(公告)日：2011-06-30
申请号：US12649847
申请日：2009-12-30
申请人： Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/412
摘要： A memory cell comprises a storage element including a transistor and an inverter. The inverter has an input coupled to a first source/drain of the transistor at a first node and has an output coupled to a gate of the transistor at a second node. The transistor has a second source/drain coupled to a voltage supply of the memory circuit. The memory cell further includes a switching element coupled to the storage element at the first node and being operative to selectively access the storage element as a function of a control signal supplied to a control input of the switching element. The storage element is operative to store at least first and second data states. The first data state is retained in the storage element by maintaining the first node at a first voltage level by leakage current and by maintaining the second node at a second voltage level by active current. The second data state is retained in the storage element by maintaining the first node at the second voltage level and the second node at the first voltage level by respective active currents.
摘要翻译：存储单元包括具有晶体管和反相器的存储元件。反相器具有在第一节点处耦合到晶体管的第一源极/漏极的输入，并且具有在第二节点处耦合到晶体管的栅极的输出。晶体管具有耦合到存储器电路的电压源的第二源极/漏极。存储单元还包括耦合到第一节点处的存储元件的开关元件，并且可操作以根据提供给开关元件的控制输入的控制信号选择性地存取存储元件。存储元件可操作以至少存储第一和第二数据状态。通过将漏电流维持在第一电压电平并通过有功电流将第二节点维持在第二电压电平，将第一数据状态保持在存储元件中。通过由相应的有效电流维持第一节点处于第二电压电平并且第二节点处于第一电压电平，第二数据状态被保留在存储元件中。

33. 发明申请

US20120075946A1 Memory Device with Phase Distribution Circuit for Controlling Relative Durations of Precharge and Active Phases 有权
标题翻译：具有相位分配电路的存储器件，用于控制预充电和有源相的相对持续时间
公开(公告)号：US20120075946A1
公开(公告)日：2012-03-29
申请号：US12893153
申请日：2010-09-29
申请人： Donald Albert Evans , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Donald Albert Evans , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C7/22 , G11C7/227
摘要： A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和相位分配电路。一方面，相位分配电路可操作以基于第一导电类型的跟踪预充电晶体管和跟踪的存储单元的相对晶体管特性来控制存储器阵列的存储周期的预充电阶段和有效相位的相应持续时间不同于第一导电类型的第二导电类型的晶体管。例如，相位分配电路可以包括用于跟踪第一导电类型的预充电晶体管的第一导电类型的第一跟踪晶体管和用于跟踪第二导电类型的存储单元晶体管的第二导电类型的第二跟踪晶体管。相对晶体管特性可以包括跟踪的预充电和存储单元晶体管的相对强度。

34. 发明申请

US20090141580A1 Reduced Leakage Driver Circuit and Memory Device Employing Same 有权
标题翻译：减少泄漏驱动电路和使用相同的存储器件
公开(公告)号：US20090141580A1
公开(公告)日：2009-06-04
申请号：US11947210
申请日：2007-11-29
申请人： Donald Albert Evans , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Donald Albert Evans , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.
摘要翻译：一种用于存储器阵列的行线驱动电路，包括多个存储器单元和耦合到存储器单元的多个行线，用于选择性地访问存储器单元包括适于连接到对应的一行行的输出级和连接到控制电路的控制电路到输出阶段。输出级在给定存储器周期的有效相位期间操作，以将对应的行线驱动为作为由驱动器电路接收的至少一个地址信号的函数的电位。控制电路至少在存储器周期的非活动阶段期间产生至少一个禁止输出级的控制信号，从而基本上消除了驱动器电路中的漏电流路径。

35. 发明授权

US07324364B2 Layout techniques for memory circuitry 有权
标题翻译：存储器电路布局技术
公开(公告)号：US07324364B2
公开(公告)日：2008-01-29
申请号：US11363010
申请日：2006-02-27
申请人： Dennis E. Dudeck , Donald A. Evans , Hai Q. Pham , Wayne E. Werner , Ronald J. Wozniak
发明人： Dennis E. Dudeck , Donald A. Evans , Hai Q. Pham , Wayne E. Werner , Ronald J. Wozniak
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C17/10 , H01L27/0207 , H01L27/112
摘要： An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of VSS planes are interconnected with the switching devices. The switching devices and the VSS planes are formed at a first level. The VSS planes can be formed as substantially complementary interlocking regions that also form functional portions of the switching devices. The switching devices can be connected between an adjacent one of the word lines and a selected one of the bit lines of an adjacent one of the bit line structures for selective electrical conduction therebetween upon activation by the adjacent one of the word lines.
摘要翻译：集成电路包括具有多个位线结构的存储器电路，每个包括至少三个位线; 在多个位置处与位线结构相交的许多字线; 以及位于这些站点的多个交换设备。一些V SS平面与开关装置互连。开关装置和V SS平面形成在第一级。 V SS平面可以形成为也形成开关装置的功能部分的基本上互补的互锁区域。开关器件可以连接在相邻的一个字线和位线结构中相邻的一个位线结构中的所选位线之间，以便在相邻的一个字线激活之后选择性地导电。

36. 发明授权

US08365044B2 Memory device with error correction based on automatic logic inversion 失效
标题翻译：基于自动逻辑反相的误差校正存储器件
公开(公告)号：US08365044B2
公开(公告)日：2013-01-29
申请号：US11738827
申请日：2007-04-23
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C17/14
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。错误校正电路被配置为在从存储器阵列检索的数据字中识别与存储器阵列中的预定缺陷位置相对应的至少一个位位置，并且通过自动反转在该存储器阵列中的逻辑值来产生校正数据字识别位位置。这种自动逻辑反转方法特别适用于校正与高密度ROM器件中的通孔缺陷和弱位缺陷相关联的输出数据错误。

37. 发明授权

US07391633B2 Accelerated searching for content-addressable memory 有权
标题翻译：加速搜索内容可寻址内存
公开(公告)号：US07391633B2
公开(公告)日：2008-06-24
申请号：US11460045
申请日：2006-07-26
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/067
摘要： A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.
摘要翻译：与包括多个匹配线的CAM电路一起使用的感测电路和连接到匹配线的多个CAM单元包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到匹配线中的对应的一个。感测电路还包括连接到对应匹配线的至少一个比较器电路，用于产生指示提供给连接到相应匹配线的至少一个给定的一个CAM单元的搜索数据和存储的数据之间的匹配的输出信号在给定的CAM单元格中。电荷共享电路用于去除相应匹配线上的电荷量，以便结合CAM单元的搜索操作来减小相应匹配线上的电压。

38. 发明申请

US20080025103A1 Accelerated Single-Ended Sensing for a Memory Circuit 有权
标题翻译：用于存储器电路的加速单端检测
公开(公告)号：US20080025103A1
公开(公告)日：2008-01-31
申请号：US11460035
申请日：2006-07-26
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C11/34
CPC分类号： G11C7/067 , G11C7/062 , G11C7/12
摘要： A single-ended sensing circuit is provided for use with a memory circuit including a plurality of bit lines and a plurality of memory cells connected to the bit lines. The sensing circuit includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to at least a given one of the bit lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the given bit line. The comparator circuit is operative to generate an output signal indicative of a logical state of a memory cell connected to the given bit line. The charge sharing circuit is operative to remove an amount of charge on the given bit line so as to reduce a voltage on the given bit line in conjunction with a read access of the memory cell.
摘要翻译：提供单端感测电路用于与包括多个位线的多个存储器单元连接的存储器电路和与位线连接的多个存储器单元。感测电路包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到位线中的至少一个给定的位线。感测电路还包括连接到给定位线的至少一个比较器电路。比较器电路用于产生指示连接到给定位线的存储器单元的逻辑状态的输出信号。电荷共享电路用于去除给定位线上的电荷量，以便结合存储器单元的读取访问来减小给定位线上的电压。

39. 发明授权

US6064231A CMOS input buffer protection circuit 失效
标题翻译： CMOS输入缓冲保护电路
公开(公告)号：US6064231A
公开(公告)日：2000-05-16
申请号：US69062
申请日：1998-04-28
申请人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
IPC分类号： H03K17/08 , H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A low voltage CMOS input buffer protection circuit that is used to protect an input buffer from any high voltage signal (e.g., 5 V) that may appear along a signal bus. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). The circuit includes a CMOS transmission gate and utilizes on-chip generated reference voltages to provide the necessary protection.
摘要翻译：低压CMOS输入缓冲保护电路，用于保护输入缓冲器免受可能沿信号总线出现的任何高电压信号（例如5 V）。保护电路也是“可热插拔”的，这意味着当不供电时（即当不存在VDD时），保护电路将不会产生任何电流。该电路包括CMOS传输门，并利用片上产生的参考电压提供必要的保护。

40. 发明授权

US5966042A Current steering output circuit with switchable shunt resistor 失效
标题翻译：电流转向输出电路，带可切换分流电阻
公开(公告)号：US5966042A
公开(公告)日：1999-10-12
申请号：US939534
申请日：1997-09-29
申请人： Wayne E. Werner , Thaddeus John Gabara , Bijit Thakorbhai Patel
发明人： Wayne E. Werner , Thaddeus John Gabara , Bijit Thakorbhai Patel
IPC分类号： G06F3/00 , H03F3/345 , H03K17/041 , H03K17/16 , H03K17/687 , H03K17/04
CPC分类号： H03K17/04106 , H03K17/162 , H03K17/6871 , Y10T307/549
摘要： A current output circuit comprises a current driver that is switchably connected across two output nodes by a switching assembly and having a switchable shunt resistor connected across the current driver. The switchable shunt resistor may be switched between a non-conducting state and a resistive conducting state. In a first data state, the current driver is connected to the output nodes by the switching assembly and the switchable shunt resistor is non-conducting so that the supplied current will flow through a load attached to the output nodes. In a second data state, the current driver is disconnected from the output nodes and the switchable shunt resistor is in a resistive conducting state. In this state the current bypasses the load and is diverted through the switchable shunt resistor. Several current drivers with appropriate switching arrangements and one or more switchable shunt resistors may be provided to allow for asymmetric current outputs in various data states.
摘要翻译：电流输出电路包括电流驱动器，其通过开关组件可切换地连接在两个输出节点上，并具有连接在当前驱动器上的可切换分流电阻器。可切换分流电阻器可以在非导通状态和电阻导通状态之间切换。在第一数据状态下，当前驱动器通过开关组件连接到输出节点，并且可切换分流电阻器不导通，使得所提供的电流将流过附接到输出节点的负载。在第二数据状态下，当前驱动器与输出节点断开，可切换分流电阻处于电阻导通状态。在这种状态下，电流旁路负载，并通过可切换的分流电阻转向。可以提供具有适当开关布置的多个电流驱动器和一个或多个可切换分流电阻器，以允许在各种数据状态下的不对称电流输出。

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