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1. 发明申请

US20120075946A1 Memory Device with Phase Distribution Circuit for Controlling Relative Durations of Precharge and Active Phases 有权
标题翻译：具有相位分配电路的存储器件，用于控制预充电和有源相的相对持续时间
公开(公告)号：US20120075946A1
公开(公告)日：2012-03-29
申请号：US12893153
申请日：2010-09-29
申请人： Donald Albert Evans , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Donald Albert Evans , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C7/22 , G11C7/227
摘要： A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和相位分配电路。一方面，相位分配电路可操作以基于第一导电类型的跟踪预充电晶体管和跟踪的存储单元的相对晶体管特性来控制存储器阵列的存储周期的预充电阶段和有效相位的相应持续时间不同于第一导电类型的第二导电类型的晶体管。例如，相位分配电路可以包括用于跟踪第一导电类型的预充电晶体管的第一导电类型的第一跟踪晶体管和用于跟踪第二导电类型的存储单元晶体管的第二导电类型的第二跟踪晶体管。相对晶体管特性可以包括跟踪的预充电和存储单元晶体管的相对强度。

2. 发明授权

US07898887B2 Sense amplifier with redundancy 有权
标题翻译：具有冗余的感应放大器
公开(公告)号：US07898887B2
公开(公告)日：2011-03-01
申请号：US12160538
申请日：2007-08-29
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C7/02 , G11C29/026 , G11C29/83
摘要： A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the sense amplifier is greater than a prescribed amount.
摘要翻译：感测放大器包括第一感测元件和对第一感测元件冗余的第二感测元件。读出放大器进一步包括开关电路，其被配置为当读出放大器的偏移大于规定量时在第一和第二感测元件之间切换。

3. 发明授权

US07826301B2 Word line driver circuit with reduced leakage 有权
标题翻译：字线驱动电路漏电减少
公开(公告)号：US07826301B2
公开(公告)日：2010-11-02
申请号：US12295745
申请日：2007-08-28
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit.
摘要翻译：一种用于存储阵列的字线驱动电路，包括多个存储器单元和耦合到存储器单元的多个字线，用于选择性地访问存储器单元包括驱动器，其适于产生作为第一组地址信号的函数的字线信号由字线驱动电路接收。电路还包括具有多个输出节点的开关电路，输出节点连接到多个字线中的相应字线，并且具有连接到驱动器的输出并适于接收字线信号的输入节点。切换电路可操作以作为至少一个控制信号的函数在存储器访问期间将字线信号引导到所选字线之一。在给定的一对存储器访问之间，输出节点和开关电路的输入节点保持相同的规定电压电平，从而基本上消除了开关电路中的漏电流路径。

4. 发明申请

US20100128549A1 Memory Circuit Having Reduced Power Consumption 有权
标题翻译：具有降低功耗的存储器电路
公开(公告)号：US20100128549A1
公开(公告)日：2010-05-27
申请号：US12276576
申请日：2008-11-24
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147 , G11C8/12
摘要： A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.
摘要翻译：具有降低的功耗的存储器电路包括多个存储器子阵列和耦合到每个存储器子阵列的共享电路。每个存储器子阵列包括至少一个行电路，至少一个列电路和可操作地耦合到行和列电路的多个存储单元。行和列电路可操作以提供对一个或多个存储器单元的选择性访问。共享电路包括存储器子阵列外部的电路，其可操作以根据提供给存储器电路的至少一个控制信号来控制存储器子阵列的一个或多个功能。存储器电路是可操作的，其中存储器子阵列中的至少一个可操作，其中一个或多个存储器子阵列供电并与未被供电的一个或多个存储器子阵列同时发送。

5. 发明授权

US07558095B2 Memory cell for content-addressable memory 有权
标题翻译：用于内容寻址内存的内存单元
公开(公告)号：US07558095B2
公开(公告)日：2009-07-07
申请号：US11743163
申请日：2007-05-02
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , Y10T29/49002
摘要： A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.
摘要翻译：用于内容寻址存储器的存储单元包括第一锁存器和第二锁存器。第一锁存器用于存储与第一存储字相关联的第一位，而第二锁存器用于存储与第二存储字相关联的第二位。第一和第二锁存器共同地包括多个锁存晶体管。每个锁存晶体管包括相应的通道。锁存晶体管的通道以大致相同的方向定向，导致非常紧凑的存储单元实现。

6. 发明申请

US20090141580A1 Reduced Leakage Driver Circuit and Memory Device Employing Same 有权
标题翻译：减少泄漏驱动电路和使用相同的存储器件
公开(公告)号：US20090141580A1
公开(公告)日：2009-06-04
申请号：US11947210
申请日：2007-11-29
申请人： Donald Albert Evans , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Donald Albert Evans , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.
摘要翻译：一种用于存储器阵列的行线驱动电路，包括多个存储器单元和耦合到存储器单元的多个行线，用于选择性地访问存储器单元包括适于连接到对应的一行行的输出级和连接到控制电路的控制电路到输出阶段。输出级在给定存储器周期的有效相位期间操作，以将对应的行线驱动为作为由驱动器电路接收的至少一个地址信号的函数的电位。控制电路至少在存储器周期的非活动阶段期间产生至少一个禁止输出级的控制信号，从而基本上消除了驱动器电路中的漏电流路径。

7. 发明申请

US20080025119A1 Accelerated Searching for Content-Addressable Memory 有权
标题翻译：加速搜索内容可寻址内存
公开(公告)号：US20080025119A1
公开(公告)日：2008-01-31
申请号：US11460045
申请日：2006-07-26
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C7/02
CPC分类号： G11C15/04 , G11C7/067
摘要： A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.
摘要翻译：与包括多个匹配线的CAM电路一起使用的感测电路和连接到匹配线的多个CAM单元包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到匹配线中的对应的一个。感测电路还包括连接到对应匹配线的至少一个比较器电路，用于产生指示提供给连接到相应匹配线的至少一个给定的一个CAM单元的搜索数据和存储的数据之间的匹配的输出信号在给定的CAM单元格中。电荷共享电路用于去除相应匹配线上的电荷量，以便结合CAM单元的搜索操作来减小相应匹配线上的电压。

8. 发明授权

US08365044B2 Memory device with error correction based on automatic logic inversion 失效
标题翻译：基于自动逻辑反相的误差校正存储器件
公开(公告)号：US08365044B2
公开(公告)日：2013-01-29
申请号：US11738827
申请日：2007-04-23
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C17/14
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。错误校正电路被配置为在从存储器阵列检索的数据字中识别与存储器阵列中的预定缺陷位置相对应的至少一个位位置，并且通过自动反转在该存储器阵列中的逻辑值来产生校正数据字识别位位置。这种自动逻辑反转方法特别适用于校正与高密度ROM器件中的通孔缺陷和弱位缺陷相关联的输出数据错误。

9. 发明授权

US07391633B2 Accelerated searching for content-addressable memory 有权
标题翻译：加速搜索内容可寻址内存
公开(公告)号：US07391633B2
公开(公告)日：2008-06-24
申请号：US11460045
申请日：2006-07-26
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/067
摘要： A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.
摘要翻译：与包括多个匹配线的CAM电路一起使用的感测电路和连接到匹配线的多个CAM单元包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到匹配线中的对应的一个。感测电路还包括连接到对应匹配线的至少一个比较器电路，用于产生指示提供给连接到相应匹配线的至少一个给定的一个CAM单元的搜索数据和存储的数据之间的匹配的输出信号在给定的CAM单元格中。电荷共享电路用于去除相应匹配线上的电荷量，以便结合CAM单元的搜索操作来减小相应匹配线上的电压。

10. 发明申请

US20080025103A1 Accelerated Single-Ended Sensing for a Memory Circuit 有权
标题翻译：用于存储器电路的加速单端检测
公开(公告)号：US20080025103A1
公开(公告)日：2008-01-31
申请号：US11460035
申请日：2006-07-26
申请人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
发明人： Dennis E. Dudeck , Donald Albert Evans , Hai Quang Pham , Wayne E. Werner , Ronald James Wozniak
IPC分类号： G11C11/34
CPC分类号： G11C7/067 , G11C7/062 , G11C7/12
摘要： A single-ended sensing circuit is provided for use with a memory circuit including a plurality of bit lines and a plurality of memory cells connected to the bit lines. The sensing circuit includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to at least a given one of the bit lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the given bit line. The comparator circuit is operative to generate an output signal indicative of a logical state of a memory cell connected to the given bit line. The charge sharing circuit is operative to remove an amount of charge on the given bit line so as to reduce a voltage on the given bit line in conjunction with a read access of the memory cell.
摘要翻译：提供单端感测电路用于与包括多个位线的多个存储器单元连接的存储器电路和与位线连接的多个存储器单元。感测电路包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到位线中的至少一个给定的位线。感测电路还包括连接到给定位线的至少一个比较器电路。比较器电路用于产生指示连接到给定位线的存储器单元的逻辑状态的输出信号。电荷共享电路用于去除给定位线上的电荷量，以便结合存储器单元的读取访问来减小给定位线上的电压。

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