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1. 发明授权

US5963083A CMOS reference voltage generator 失效
标题翻译： CMOS参考电压发生器
公开(公告)号：US5963083A
公开(公告)日：1999-10-05
申请号：US067818
申请日：1998-04-28
申请人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
IPC分类号： G05F3/24 , H03K17/08 , H03K19/003 , G05F1/10
CPC分类号： G05F3/247
摘要： A CMOS voltage generator for providing a reference voltage VDD2 that will track the low level power supply voltage VDD (approximately 3.0V-3.6V) as long as the power supply is present. When VDD is not present (defined as at "hot pluggable" condition), the voltage generator is configured to maintain a "protection" output voltage less than the relatively high voltage (approximately 5V) that may appear along a circuit signal bus. In particular, the circuit includes at least a pair of diode-connected N-channel devices disposed between the signal bus line and the output voltage terminal to provide the necessary protection.
摘要翻译： CMOS电压发生器，用于提供参考电压VDD2，只要存在电源，该参考电压VDD2将跟踪低电平电源电压VDD（约3.0V-3.6V）。当VDD不存在（定义为“可热插拔”状态）时，电压发生器被配置为保持“保护”输出电压小于沿电路信号总线出现的较高电压（约5V）。特别地，该电路包括设置在信号总线与输出电压端子之间的至少一对二极管连接的N沟道器件，以提供必要的保护。

2. 发明授权

US6014039A CMOS high voltage drive output buffer 失效
标题翻译： CMOS高电压驱动输出缓冲器
公开(公告)号：US6014039A
公开(公告)日：2000-01-11
申请号：US67936
申请日：1998-04-28
申请人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
IPC分类号： H03K17/08 , H03K19/003 , H03K19/0175 , H03K19/0948 , H03K19/0185
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A CMOS high voltage drive output buffer that protects the drive stage from seeing relatively high voltages (e.g., 5 V) during "hot pluggable" conditions (that is, when the reference voltage VDD is not present). A transmission gate and clamping transistors are disposed around the output devices to provide the requisite protection. A backgate bias generator for use with P-channel devices is also disclosed that is capable of withstanding "hot pluggable" conditions.
摘要翻译： CMOS高电压驱动输出缓冲器，用于在“可热插拔”状态（即当不存在参考电压VDD时）保护驱动级不会看到相对较高的电压（例如5 V）。传输栅极和钳位晶体管围绕输出器件设置以提供必要的保护。还公开了一种用于P沟道器件的背栅偏置发生器，其能够承受“可热插拔”的条件。

3. 发明授权

US6064231A CMOS input buffer protection circuit 失效
标题翻译： CMOS输入缓冲保护电路
公开(公告)号：US6064231A
公开(公告)日：2000-05-16
申请号：US69062
申请日：1998-04-28
申请人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
IPC分类号： H03K17/08 , H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A low voltage CMOS input buffer protection circuit that is used to protect an input buffer from any high voltage signal (e.g., 5 V) that may appear along a signal bus. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). The circuit includes a CMOS transmission gate and utilizes on-chip generated reference voltages to provide the necessary protection.
摘要翻译：低压CMOS输入缓冲保护电路，用于保护输入缓冲器免受可能沿信号总线出现的任何高电压信号（例如5 V）。保护电路也是“可热插拔”的，这意味着当不供电时（即当不存在VDD时），保护电路将不会产生任何电流。该电路包括CMOS传输门，并利用片上产生的参考电压提供必要的保护。

4. 发明授权

US5952866A CMOS output buffer protection circuit 失效
标题翻译： CMOS输出缓冲保护电路
公开(公告)号：US5952866A
公开(公告)日：1999-09-14
申请号：US069049
申请日：1998-04-28
申请人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
IPC分类号： H03K17/08 , H03K19/003 , H03K19/0175 , H03L5/00
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A low voltage CMOS output buffer protection circuit is configured to protect an associated output buffer from any high voltage signals (e.g., 5V) that may appear along a signal bus line. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). An on-chip reference voltage generator is used to provide a reference voltage VDD2 that will be essentially equal to VDD as long as VDD is present. When VDD is not present, VDD2 will track the signal appearing along the signal bus (PAD), remaining at least two diode drops below the PAD voltage.
摘要翻译：低电压CMOS输出缓冲保护电路被配置为保护相关联的输出缓冲器免受可能沿信号总线出现的任何高电压信号（例如5V）。保护电路也是“可热插拔”的，这意味着当不供电时（即当不存在VDD时），保护电路将不会产生任何电流。片上参考电压发生器用于提供基本上等于VDD的参考电压VDD2，只要存在VDD即可。当VDD不存在时，VDD2将跟踪沿着信号总线（PAD）出现的信号，至少保持两个二极管降低到PAD电压以下。

5. 发明授权

US5847556A Precision current source 失效
标题翻译：精密电流源
公开(公告)号：US5847556A
公开(公告)日：1998-12-08
申请号：US994019
申请日：1997-12-18
申请人： Makeshwar Kothandaraman , Bijit Thakorbhai Patel , David Arthur Rich
发明人： Makeshwar Kothandaraman , Bijit Thakorbhai Patel , David Arthur Rich
IPC分类号： G05F3/26 , H03F3/343 , G05F3/16
CPC分类号： G05F3/262
摘要： A current source includes a first current mirror and a second current mirror that share a common current path. The current in the common current path mirrors a current of a current reference connected to the first current mirror. A current in an output current path of the second current mirror mirrors the current of the common current path. A first feedback loop controls the current in the common current path and a second feedback loop matches a voltage of the common current path with an output voltage. The cooperation of the first and second feedback loops ensures that the output current replicates the current of the current reference even when an voltage of the current source is close to the supply voltage. Thus, the voltage swing of the current source output voltage is increased and a precision current source is provided even when the output voltage is close to the supply voltage.
摘要翻译：电流源包括共享公共电流路径的第一电流镜和第二电流镜。公共电流通路中的电流反映连接到第一电流镜的电流基准的电流。第二电流镜的输出电流路径中的电流反映了公共电流路径的电流。第一反馈环路控制公共电流路径中的电流，第二反馈环路将公共电流路径的电压与输出电压相匹配。第一和第二反馈回路的协作确保即使当电流源的电压接近电源电压时，输出电流复制电流参考电流。因此，即使当输出电压接近电源电压时，电流源输出电压的电压摆幅也增加，并提供精确的电流源。

6. 发明授权

US6107882A Amplifier having improved common mode voltage range 失效
标题翻译：具有改善的共模电压范围的放大器
公开(公告)号：US6107882A
公开(公告)日：2000-08-22
申请号：US65255
申请日：1998-04-23
申请人： Thaddeus John Gabara , Makeshwar Kothandaraman , Bijit Thakorbhai Patel
发明人： Thaddeus John Gabara , Makeshwar Kothandaraman , Bijit Thakorbhai Patel
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45237 , H03F3/45479 , H03F3/4565 , H03F3/45659 , H03F2203/45352 , H03F2203/45371 , H03F2203/45418 , H03F2203/45424
摘要： Embodiments of the invention include an amplifier such as a differential amplifier having an improved common mode voltage range (CMVR). The amplifier includes a translator coupled to a second stage amplifying circuitry wherein the translator uses feedback and a parallel connection of input devices to improve the common mode voltage range of the amplifier while providing for enablement of the circuit functionality. The translator uses parallel connections of N-channel and P-channel devices such as transistors to extract alternating current (ac) signals riding on a common mode voltage and to translate the extracted ac signals to ride on a constant reference voltage (V.sub.ref). The translated signals are then amplified in a conventional manner, such as by a gate thresholding or a self-biasing technique. An input sensing circuit within the translator provides an offset detection signal to a correction circuit, also within the translator. The correction circuit compares the signal with an applied reference signal (V.sub.ref) and, based thereon, applies a correction signal to the input sensing circuit. With the benefit of such correction signals, the input sensing circuit translates an input signal with a large common mode voltage range to an output signal that rides on the dc voltage that is approximately equal to the reference signal, V.sub.ref.
摘要翻译：本发明的实施例包括具有改进的共模电压范围（CMVR）的诸如差分放大器的放大器。放大器包括耦合到第二级放大电路的转换器，其中转换器使用反馈和输入装置的并联连接来改善放大器的共模电压范围，同时提供电路功能的实现。转换器使用N沟道和P沟道器件（例如晶体管）的并联连接来提取乘以共模电压的交流（ac）信号，并将提取的交流信号转换为乘以恒定参考电压（Vref）。然后，以常规方式，例如通过门限阈值或自偏置技术来放大转换后的信号。翻译器内的输入感测电路还向翻译器内的校正电路提供偏移检测信号。校正电路将信号与施加的参考信号（Vref）进行比较，并且基于此，将校正信号施加到输入感测电路。利用这种校正信号，输入感测电路将具有大共模电压范围的输入信号转换成乘以大约等于参考信号Vref的直流电压的输出信号。

7. 发明授权

US5926056A Voltage tolerant output buffer 失效
标题翻译：耐压输出缓冲器
公开(公告)号：US5926056A
公开(公告)日：1999-07-20
申请号：US5751
申请日：1998-01-12
申请人： Bernard Lee Morris , Bijit Thakorbhai Patel
发明人： Bernard Lee Morris , Bijit Thakorbhai Patel
IPC分类号： H01L27/04 , H01L21/822 , H03K19/003 , H03K19/0175 , H03L5/00 , H03B1/00
CPC分类号： H03K19/00315
摘要： An integrated circuit output buffer has an improved tolerance to voltage levels that are greater than the power supply voltage level at which the IC is designed to operate. A first transmission gate transistor (110), typically p-channel, is connected between an output conductor (101) and a resistor (108) at a given node (114). The node is also connected to the gate of a second transmission gate transistor (105), typically also p-channel. The resistor pulls the given node towards a power supply voltage level (e.g., ground), so that the second transmission gate transistor conducts in normal operation. To prevent the node from reaching ground, at least one diode-like voltage-dropping device (201, 202) is connected in series with the resistor.
摘要翻译：集成电路输出缓冲器具有比电容器设计为工作的电源电压电平更高的对电压电平的容限。典型的p沟道的第一传输门晶体管（110）连接在给定节点（114）处的输出导体（101）和电阻器（108）之间。节点也连接到第二传输门晶体管（105）的栅极，通常也是p沟道。电阻器将给定节点拉向电源电压电平（例如，接地），使得第二传输栅极晶体管在正常操作中导通。为了防止节点到达地，至少一个二极管状降压装置（201,202）与电阻串联。

8. 发明授权

US5973530A Low power, high voltage-tolerant bus holder circuit in low voltage technology 失效
标题翻译：低功耗，高耐压母线电路的低压技术
公开(公告)号：US5973530A
公开(公告)日：1999-10-26
申请号：US87303
申请日：1998-05-29
申请人： Bernard Lee Morris , Bijit Thakorbhai Patel
发明人： Bernard Lee Morris , Bijit Thakorbhai Patel
IPC分类号： H03K3/012 , H03K3/356 , H03K5/007 , H03K19/003 , H03K19/0948 , H03K19/0175
CPC分类号： H03K3/356165 , H03K19/00315 , H03K3/012 , H03K5/007
摘要： An integrated, low power bus holder circuit implemented in low voltage technology is capable of interfacing with a relatively high voltage bus. In an illustrative embodiment, the bus holder circuit includes a first inverter for inverting a logic voltage present on a data bus and a second inverter for inverting the output of the first inverter. The second inverter is comprised of a series string of first and second pFETS and first and second nFETS, with the gates of the first pFET and first nFET coupled to the output of the first inverter. The data bus is coupled to a first circuit node between the second nFET and second pFET, and the bus logic level is maintained thereat. A third pFET is coupled to the second inverter and conducts current when a high logic voltage is present on the bus. A resistance device is coupled between a drain of the third pFET and a point of low reference potential. Advantageously, the circuit arrangement of the illustrative embodiment does not draw any DC power since it avoids the use of a separate, DC power consuming biasing circuit to bias the third pFET. A fourth pFET is preferably employed to eliminate leakage current in the first inverter.
摘要翻译：在低电压技术中实现的集成的低功率总线保持器电路能够与相对高压的总线接口。在说明性实施例中，总线保持器电路包括用于反转存在于数据总线上的逻辑电压的第一反相器和用于反转第一反相器的输出的第二反相器。第二反相器由串联的第一和第二pFET以及第一和第二nFETS组成，其中第一pFET和第一nFET的栅极耦合到第一反相器的输出。数据总线耦合到第二nFET和第二pFET之间的第一电路节点，并且总线逻辑电平被保持在那里。当总线上存在高逻辑电压时，第三pFET耦合到第二反相器并传导电流。电阻器件耦合在第三pFET的漏极和低参考电位点之间。有利地，说明性实施例的电路装置不会产生任何DC电力，因为它避免使用单独的DC功率消耗偏置电路来偏置第三pFET。优选使用第四pFET来消除第一反相器中的漏电流。

9. 发明授权

US5966042A Current steering output circuit with switchable shunt resistor 失效
标题翻译：电流转向输出电路，带可切换分流电阻
公开(公告)号：US5966042A
公开(公告)日：1999-10-12
申请号：US939534
申请日：1997-09-29
申请人： Wayne E. Werner , Thaddeus John Gabara , Bijit Thakorbhai Patel
发明人： Wayne E. Werner , Thaddeus John Gabara , Bijit Thakorbhai Patel
IPC分类号： G06F3/00 , H03F3/345 , H03K17/041 , H03K17/16 , H03K17/687 , H03K17/04
CPC分类号： H03K17/04106 , H03K17/162 , H03K17/6871 , Y10T307/549
摘要： A current output circuit comprises a current driver that is switchably connected across two output nodes by a switching assembly and having a switchable shunt resistor connected across the current driver. The switchable shunt resistor may be switched between a non-conducting state and a resistive conducting state. In a first data state, the current driver is connected to the output nodes by the switching assembly and the switchable shunt resistor is non-conducting so that the supplied current will flow through a load attached to the output nodes. In a second data state, the current driver is disconnected from the output nodes and the switchable shunt resistor is in a resistive conducting state. In this state the current bypasses the load and is diverted through the switchable shunt resistor. Several current drivers with appropriate switching arrangements and one or more switchable shunt resistors may be provided to allow for asymmetric current outputs in various data states.
摘要翻译：电流输出电路包括电流驱动器，其通过开关组件可切换地连接在两个输出节点上，并具有连接在当前驱动器上的可切换分流电阻器。可切换分流电阻器可以在非导通状态和电阻导通状态之间切换。在第一数据状态下，当前驱动器通过开关组件连接到输出节点，并且可切换分流电阻器不导通，使得所提供的电流将流过附接到输出节点的负载。在第二数据状态下，当前驱动器与输出节点断开，可切换分流电阻处于电阻导通状态。在这种状态下，电流旁路负载，并通过可切换的分流电阻转向。可以提供具有适当开关布置的多个电流驱动器和一个或多个可切换分流电阻器，以允许在各种数据状态下的不对称电流输出。

10. 发明授权

US06621360B1 Extended frequency range voltage-controlled oscillator 有权
标题翻译：扩展频率范围压控振荡器
公开(公告)号：US06621360B1
公开(公告)日：2003-09-16
申请号：US10056412
申请日：2002-01-22
申请人： Chao Xu , Bijit Thakorbhai Patel
发明人： Chao Xu , Bijit Thakorbhai Patel
IPC分类号： H03B2700
CPC分类号： H03L7/0995 , H03K3/0322 , H03K2005/00026 , H03L2207/06
摘要： VCO frequency is continuously variable through a wide frequency range in proportion to a first control voltage VC produced by a PLL containing the VCO. A second control voltage NVC is produced as a monotonically decreasing function of VC. A first current I0 is produced in proportion to VC and a second current I1 is produced in proportion to NVC. I1 is subtracted from I0, producing a control current IC=I0-I1 which is applied to the VCO.
摘要翻译： VCO频率与由包含VCO的PLL产生的第一控制电压VC成比例的宽频率范围可连续变化。产生第二控制电压NVC作为VC的单调递减函数。与VC成比例地产生第一电流I0，并且与NVC成比例地产生第二电流I1。从I0减去I1，产生施加到VCO的控制电流IC = I0-I1。

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