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1. 发明授权

US08847657B2 Low power receiver for implementing a high voltage interface implemented with low voltage devices 有权
标题翻译：低功率接收器，用于实现采用低电压器件实现的高压接口
公开(公告)号：US08847657B2
公开(公告)日：2014-09-30
申请号：US13530426
申请日：2012-06-22
申请人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
发明人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/0013 , H03K19/018507
摘要： An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
摘要翻译：一种包括第一级和第二级的装置。第一级可以被配置为响应于具有从焊盘接收到的第二电压的输入信号而产生具有第一电压的中间信号。第二级可以被配置为响应于第一电压而产生核心电压。从焊盘接收的电压可以在符合一个或多个公布的接口规范的电压下工作。

2. 发明授权

US08487691B1 AC noise suppression from a bias signal in high voltage supply/low voltage device 有权
标题翻译：高压电源/低压器件偏置信号的交流噪声抑制
公开(公告)号：US08487691B1
公开(公告)日：2013-07-16
申请号：US13494282
申请日：2012-06-12
申请人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
发明人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
IPC分类号： G05F1/10
CPC分类号： H03F1/26 , H03F3/2171 , H03K19/00346
摘要： An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.
摘要翻译：一种包括第一电路，第二电路和第三电路的装置。第一电路可以被配置为产生第一控制电压和第二控制电压。第二电路可以被配置为响应于第一控制电压和第二控制电压而产生偏置信号。第三电路可以被配置为响应于偏置信号产生滤波信号。滤波后的信号可以被添加到第一控制电压和第二控制电压，以在产生偏置信号时提供AC噪声抑制。

3. 发明申请

US20110187431A1 Voltage Level Translator Circuit 有权
标题翻译：电压电平转换器电路
公开(公告)号：US20110187431A1
公开(公告)日：2011-08-04
申请号：US12598352
申请日：2008-12-29
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/356113 , H03K3/0375
摘要： A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).
摘要翻译：电压转换器电路（320）包括适于接收参考第一电压源（VDD核心）的输入信号的输入级（322），适于连接到第二电压源（VDD33）的锁存器（326）至少临时存储输入信号的逻辑状态，以及耦合在输入级（322）和锁存器（326）之间的电压钳位（324）。电压钳（322）用于将锁存器（326）两端的最大电压设定为第一规定电平，并将输入级两端的最大电压设定为第二规定电平。电压转换器电路（320）在闩锁（326）和电压钳（324）之间的连接处产生第一输出信号（II）。电压转换器电路在电压钳位器（324）和输入级（322）之间的接点处产生第二输出信号（15）。

4. 发明申请

US20100271118A1 I/O Buffer with Low Voltage Semiconductor Devices 失效
标题翻译：带低压半导体器件的I / O缓冲器
公开(公告)号：US20100271118A1
公开(公告)日：2010-10-28
申请号：US12428556
申请日：2009-04-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
IPC分类号： G05F1/10
CPC分类号： H03K17/0822 , H03K19/018528
摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
摘要翻译：所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。从缓冲器的工作电压产生第一和第二偏置电压。从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压缓冲。第三和第四偏置电压分别提供给第一和第二过压保护电路。

5. 发明授权

US07642807B2 Multiple-mode compensated buffer circuit 有权
标题翻译：多模式补偿缓冲电路
公开(公告)号：US07642807B2
公开(公告)日：2010-01-05
申请号：US11768496
申请日：2007-06-26
申请人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03K17/16
CPC分类号： H03K19/00376
摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.
摘要翻译：以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。输出块的各输出端连接在一起形成缓冲电路的输出。输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等效于第一模式中的二进制码字的算术移位。

6. 发明申请

US20080074171A1 Method and Apparatus for Improving Reliability of an Integrated Circuit Having Multiple Power Domains 有权
标题翻译：提高具有多个电源域的集成电路的可靠性的方法和装置
公开(公告)号：US20080074171A1
公开(公告)日：2008-03-27
申请号：US11535198
申请日：2006-09-26
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , H01L27/0251 , H03K19/00315
摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.
摘要翻译：具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

7. 发明申请

US20070229157A1 Circuit having enhanced input signal range 有权
标题翻译：电路具有增强的输入信号范围
公开(公告)号：US20070229157A1
公开(公告)日：2007-10-04
申请号：US11393171
申请日：2006-03-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F2200/513 , H03F2200/78 , H03F2203/45314 , H03F2203/45361 , H03F2203/45552 , H03F2203/45684
摘要： A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors operative to receive the first and second signals, respectively, each of the first and second transistors having a first threshold voltage associated therewith, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and being operative to receive the difference signal and to generate an output signal of the circuit, the output signal being indicative of the difference signal and being referenced to the first voltage. The circuit is configured to accept the first and second signals having a voltage swing which is potentially greater than a supply voltage of the circuit.
摘要翻译：具有增强的输入信号范围的电路包括差分放大器，其可操作以接收至少第一和第二信号并放大第一和第二信号之间的差。差分放大器在其输出处产生差分信号，其作为第一和第二信号之间的差异的函数。差分放大器包括具有至少第一和第二晶体管的输入级，其中第一和第二晶体管分别用于接收第一和第二信号，第一和第二晶体管中的每一个具有与之相关联的第一阈值电压，并且负载包括至少第三和第四晶体管具有与其相关联的第二阈值电压，所述第一阈值电压大于所述第二阈值电压。电路还包括耦合到差分放大器的输出级，并且可操作以接收差分信号并产生电路的输出信号，输出信号指示差分信号并参考第一电压。电路被配置为接受具有潜在地大于电路的电源电压的电压摆幅的第一和第二信号。

8. 发明授权

US07276957B2 Floating well circuit having enhanced latch-up performance 失效
标题翻译：具有增强的闭锁性能的浮动井回路
公开(公告)号：US07276957B2
公开(公告)日：2007-10-02
申请号：US11239840
申请日：2005-09-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Duane J. Loeper , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Duane J. Loeper , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.
摘要翻译：用于限定其中形成有至少一个金属氧化物半导体器件的浮动阱的电压电位的电路包括感测电路，其可操作以检测浮动阱连接到的节点处的电压，并产生指示性的控制信号节点处的电压是否基本上在电压范围内。电压范围的较低值基本上等于低于电路的第一电源电压的阈值电压。电压范围的较高值基本上等于高于第一电源电压的阈值电压。用于定义浮动阱的电压电位的电路还包括电压发生器电路，其操作以接收控制信号并产生用于响应于控制信号设置阱的电压电位的偏置信号，偏置信号被控制在整个电压范围。

9. 发明申请

US20050156629A1 HIGH CURRENT 5V TOLERANT BUFFER USING A 2.5 VOLT POWER SUPPLY 失效
标题翻译：使用2.5伏电源的高电流5V耐受缓冲器
公开(公告)号：US20050156629A1
公开(公告)日：2005-07-21
申请号：US10759253
申请日：2004-01-20
申请人： Carol Huber , Bernard Morris , Makeshwar Kothandaraman , Yehuda Smooha
发明人： Carol Huber , Bernard Morris , Makeshwar Kothandaraman , Yehuda Smooha
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： Using at best a 2.5V nominal power supply, 3.3V technology can be used to implement a 5V tolerant open drain output buffer. High voltage and/or current tolerance is achieved with only the 2.5V power supply. A p-channel FET transistor is connected between a power supply and a node, which in turn is connected to a node between two series output FET transistors. The first transistor is connected between the PAD and node, and the second transistor is connected between the node and ground. The gate of the second transistor is driven from another node formed between a series string of a p-channel FET transistor and an n-channel FET transistor. The other side of the first transistor is connected to the power supply, and the other side of the second transistor is connected to ground. The gates of the transistors the inverter are tied together and driven by an applied signal.
摘要翻译：最多使用2.5V标称电源，3.3V技术可用于实现5V容限的开漏输出缓冲器。仅使用2.5V电源即可实现高电压和/或电流公差。 p沟道FET晶体管连接在电源和节点之间，而节点又连接到两个串联输出FET晶体管之间的节点。第一晶体管连接在PAD和节点之间，第二晶体管连接在节点和地之间。第二晶体管的栅极由形成在p沟道FET晶体管的串联串和n沟道FET晶体管之间的另一个节点驱动。第一晶体管的另一侧连接到电源，第二晶体管的另一侧连接到地。晶体管的栅极将反相器连接在一起并由施加的信号驱动。

10. 发明授权

US5847556A Precision current source 失效
标题翻译：精密电流源
公开(公告)号：US5847556A
公开(公告)日：1998-12-08
申请号：US994019
申请日：1997-12-18
申请人： Makeshwar Kothandaraman , Bijit Thakorbhai Patel , David Arthur Rich
发明人： Makeshwar Kothandaraman , Bijit Thakorbhai Patel , David Arthur Rich
IPC分类号： G05F3/26 , H03F3/343 , G05F3/16
CPC分类号： G05F3/262
摘要： A current source includes a first current mirror and a second current mirror that share a common current path. The current in the common current path mirrors a current of a current reference connected to the first current mirror. A current in an output current path of the second current mirror mirrors the current of the common current path. A first feedback loop controls the current in the common current path and a second feedback loop matches a voltage of the common current path with an output voltage. The cooperation of the first and second feedback loops ensures that the output current replicates the current of the current reference even when an voltage of the current source is close to the supply voltage. Thus, the voltage swing of the current source output voltage is increased and a precision current source is provided even when the output voltage is close to the supply voltage.
摘要翻译：电流源包括共享公共电流路径的第一电流镜和第二电流镜。公共电流通路中的电流反映连接到第一电流镜的电流基准的电流。第二电流镜的输出电流路径中的电流反映了公共电流路径的电流。第一反馈环路控制公共电流路径中的电流，第二反馈环路将公共电流路径的电压与输出电压相匹配。第一和第二反馈回路的协作确保即使当电流源的电压接近电源电压时，输出电流复制电流参考电流。因此，即使当输出电压接近电源电压时，电流源输出电压的电压摆幅也增加，并提供精确的电流源。

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