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1. 发明申请

US20080117702A1 INTEGRATED CIRCUIT HAVING A MEMORY WITH PROCESS-VOLTAGE-TEMPERATURE CONTROL 有权
标题翻译：具有过程电压控制的存储器的集成电路
公开(公告)号：US20080117702A1
公开(公告)日：2008-05-22
申请号：US11860891
申请日：2007-09-25
申请人： Matthew R. Henry , Douglas D. Lopata , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Matthew R. Henry , Douglas D. Lopata , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： G11C7/04 , G11C7/02
CPC分类号： G11C7/04 , G11C7/22 , G11C2207/104
摘要： Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.
摘要翻译：本发明的某些实施例提供一种集成电路（IC），其具有可操作地耦合到PVT（过程电压 - 温度）源和可调节存储器的处理器。处理器从源头接收表征当前PVT条件的输入，并且基于该输入生成用于存储器的命令。响应于该命令，存储器调整其内部电路结构，时钟速度和/或工作电压以优化其对于当前PVT条件的性能。有利地，调整存储器以使其能够维持其功能并在不利的PVT条件下提供可接受的性能水平的能力在选择电路设计选项方面提供了额外的灵活性，其可以产生区域节省和/或增加可接受的IC的产量制造。

2. 发明授权

US07313713B2 Sequential/combinational logic transistor segregation for standby power and performance optimization 失效
标题翻译：用于待机功率和性能优化的顺序/组合逻辑晶体管隔离
公开(公告)号：US07313713B2
公开(公告)日：2007-12-25
申请号：US10923403
申请日：2004-08-20
申请人： Eugene F. Weber , Matthew R. Henry
发明人： Eugene F. Weber , Matthew R. Henry
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A method and apparatus for powering digital logic circuits that provides low power consumption while maintaining high performance. The circuit is divided into logic elements necessary for maintaining the state of the circuit and those that are not. The state-maintaining logic uses low-leakage, low performance transistors, and is continually powered. The remainder of the circuit uses standard transistors, i.e., high performance, high-leakage transistors, and is only powered when the circuit is active, i.e., not in a standby mode. Two power rails are used, one for the state maintaining components and one for the non-state-maintaining components. The state-maintaining logic is functionally separated from the remainder of the circuit when the remainder of the circuit is being powered up or down to avoid short-circuiting any elements. Typical state-maintaining components are sequential logic gates. Typical non-state maintaining components are combinational logic gates. A typical functional isolation gates is a NOR gate.
摘要翻译：为维持高性能而提供低功耗的数字逻辑电路供电的方法和装置。电路被分为维持电路状态和不使用电路所需的逻辑元件。状态维护逻辑使用低泄漏，低性能晶体管，并且不断供电。电路的其余部分使用标准晶体管，即高性能，高泄漏晶体管，并且仅在电路处于活动状态时被供电，即不处于待机模式。使用两个电源轨，一个用于状态维护组件，一个用于非状态维护组件。当电路的其余部分上电或下电时，状态保持逻辑在功能上与电路的其余部分分离，以避免短路任何元件。典型的状态维护组件是顺序逻辑门。典型的非状态维护组件是组合逻辑门。典型的功能隔离门是NOR门。

3. 发明授权

US5381420A Decoupled scan path interface 失效
标题翻译：解耦扫描路径接口
公开(公告)号：US5381420A
公开(公告)日：1995-01-10
申请号：US173393
申请日：1993-12-22
申请人： Matthew R. Henry
发明人： Matthew R. Henry
IPC分类号： G01R31/3185 , G06F11/28
CPC分类号： G01R31/318552
摘要： An interface to internal scan paths within an IC for synchronizing a test clock and a system clock without adversely affecting their operation. The test clock provides input test data (TDI) to the interface and receives output test data (TDO) from the interface at the test clock rate. The system clock drives the test data through the scan path at the system clock rate. The two clocks are "decoupled" in that they run independently, being synchronized by the interface for clocking the test data into, through and out of the scan path. In effect, the interface decouples the internal scan paths driven by the system clock from the test logic driven by the test clock. This feature enables the IC to be tested "at speed" and provides for synchronization between the test clock and system clock over a wide range of test clock frequencies.
摘要翻译： IC内部扫描路径的接口，用于同步测试时钟和系统时钟，而不会对其操作产生不利影响。测试时钟为接口提供输入测试数据（TDI），并以测试时钟速率从接口接收输出测试数据（TDO）。系统时钟以系统时钟速率通过扫描路径驱动测试数据。这两个时钟是“去耦合”的，因为它们独立运行，被接口同步，用于将测试数据记录到扫描路径中，进出扫描路径。实际上，接口将由系统时钟驱动的内部扫描路径与由测试时钟驱动的测试逻辑分离。该功能使IC能够以“速度”进行测试，并在宽范围的测试时钟频率上提供测试时钟和系统时钟之间的同步。

4. 发明授权

US4791603A Dynamically reconfigurable array logic 失效
标题翻译：动态可重构阵列逻辑
公开(公告)号：US4791603A
公开(公告)日：1988-12-13
申请号：US886700
申请日：1986-07-18
申请人： Matthew R. Henry
发明人： Matthew R. Henry
IPC分类号： G06F9/22 , H03K19/177 , G06F7/38 , H03K19/20
CPC分类号： H03K19/17752 , H03K19/17704 , H03K19/1776
摘要： A dynamically reconfigurable array logic (DRAL) is capable of in-system logical reconfiguration in real time and comprises a RAM programmable logic array of bits, each bit comprising a fuse connection between logic elements. I/O means are coupled to the RAM programmable logic array for logical selection of registered output. A first register is coupled for receiving data and high-level commands. A sequencer includes a pair of up/down counters and functions to generate addresses. A timing device controls DMA transfers and issues READ and WRITE strobes. A second register monitors outputs and functions as a comparator, in a first mode, and functions to load outputs during specified time intervals in a second mode.
摘要翻译：动态可重配置阵列逻辑（DRAL）能够实时地进行系统内逻辑重配置，并且包括RAM的可编程逻辑阵列阵列，每个位包括逻辑元件之间的熔丝连接。 I / O装置耦合到RAM可编程逻辑阵列，用于逻辑选择注册输出。第一个寄存器用于接收数据和高级命令。定序器包括一对增/减计数器和产生地址的功能。定时设备控制DMA传输并发出READ和WRITE选通信号。第二个寄存器在第一模式下监视输出和功能作为比较器，并且用于在第二模式下在指定的时间间隔期间加载输出。

5. 发明申请

US20090112959A1 Single-cycle FFT butterfly calculator 有权
标题翻译：单循环FFT蝶形计算器
公开(公告)号：US20090112959A1
公开(公告)日：2009-04-30
申请号：US11982228
申请日：2007-10-31
申请人： Matthew R. Henry
发明人： Matthew R. Henry
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： In accordance with exemplary embodiments, a Fast Fourier Transform (FFT) architecture includes elements that perform a radix-2 FFT butterfly in one processor clock cycle at steady state. Some exemplary implementations of the FFT architecture incorporate register and data path elements that relieve memory bandwidth limitations by pairing operands consumed by and results generated by two adjacent butterflies in the overall N-point FFT operation.
摘要翻译：根据示例性实施例，快速傅里叶变换（FFT）架构包括在稳定状态下在一个处理器时钟周期中执行基2 FFT蝶形的元件。 FFT架构的一些示例性实现包括寄存器和数据路径元素，其通过将由两个相邻蝴蝶产生的操作数与由N点FFT运算组成的操作数进行配对来减轻存储器带宽限制。

6. 发明申请

US20080286880A1 Methods and Systems for Nanoparticle Enhancement of Signals 审中-公开
标题翻译：纳米粒子增强信号的方法与系统
公开(公告)号：US20080286880A1
公开(公告)日：2008-11-20
申请号：US11571642
申请日：2005-07-05
申请人： Samer Al-Murrani , Stephen J. Fonash , Matthew R. Henry , Ali Kaan Kalkan , Daniel Krissinger , Terry Rager
发明人： Samer Al-Murrani , Stephen J. Fonash , Matthew R. Henry , Ali Kaan Kalkan , Daniel Krissinger , Terry Rager
IPC分类号： G01N21/75
CPC分类号： G01N21/658 , B82Y15/00 , B82Y30/00 , G01N21/6428 , G01N21/648
摘要： Methods and systems for utilizing metal nanoparticles to enhance optical (UV, visible, and IR, as appropriate) signals from a reporting entity are presented. The methods and systems of this invention do not require the nanoparticles to be attached or adhered to a surface, assembled in a matrix or coated with a spacer coating.
摘要翻译：提出了利用金属纳米粒子增强来自报告实体的光学（UV，可视和IR，适当）信号的方法和系统。本发明的方法和系统不需要将纳米颗粒附着或粘附到表面，组装在基质中或用间隔剂涂层涂覆。

7. 发明授权

US6121814A Tri-state bus controller 有权
标题翻译：三态总线控制器
公开(公告)号：US6121814A
公开(公告)日：2000-09-19
申请号：US169794
申请日：1998-10-09
申请人： Matthew R. Henry
发明人： Matthew R. Henry
IPC分类号： H03K3/84
CPC分类号： G06F13/00 , G06F13/4072
摘要： A bus master controller comprising a plurality of logic modules, each module coupled to a separate bus driver circuit. The logic module operates using a "break-before-make" protocol derived from a finite state machine, delay element and exclusive-OR gate. The finite state machine generates a predetermined sequence that requires an "assert" signal to always be delayed with respect to a "de-assert" signal, thus eliminating the possibility that more than one set of bus drivers will be coupled to the bus at any one time.
摘要翻译：总线主控制器包括多个逻辑模块，每个模块耦合到单独的总线驱动器电路。逻辑模块使用从有限状态机，延迟元件和异或门导出的“断开 - 制造”协议进行操作。有限状态机产生一个预定的序列，该序列需要相对于“去断言”信号总是被延迟的“断言”信号，从而消除了多于一组总线驱动器将以任何方式耦合到总线的可能性一次。

8. 发明授权

US07847349B2 Single-cycle FFT butterfly calculator 有权
标题翻译：单循环FFT蝶形计算器
公开(公告)号：US07847349B2
公开(公告)日：2010-12-07
申请号：US11982228
申请日：2007-10-31
申请人： Matthew R. Henry
发明人： Matthew R. Henry
IPC分类号： H01L29/94 , H01L23/62 , H01L21/8238
CPC分类号： G06F17/142
摘要： In accordance with exemplary embodiments, a Fast Fourier Transform (FFT) architecture includes elements that perform a radix-2 FFT butterfly in one processor clock cycle at steady state. Some exemplary implementations of the FFT architecture incorporate register and data path elements that relieve memory bandwidth limitations by pairing operands consumed by and results generated by two adjacent butterflies in the overall N-point FFT operation.
摘要翻译：根据示例性实施例，快速傅里叶变换（FFT）架构包括在稳定状态下在一个处理器时钟周期中执行基2 FFT蝶形的元件。 FFT架构的一些示例性实现包括寄存器和数据路径元素，其通过将由两个相邻蝴蝶产生的操作数与由N点FFT运算组成的操作数进行配对来减轻存储器带宽限制。

9. 发明授权

US06928057B2 Translation system and related method for use with a communication device 失效
标题翻译：用于通信设备的翻译系统及相关方法
公开(公告)号：US06928057B2
公开(公告)日：2005-08-09
申请号：US09777054
申请日：2001-02-05
申请人： William R. Bullman , Matthew R. Henry , Ryan S. Holmqvist , Steven E. Strauss
发明人： William R. Bullman , Matthew R. Henry , Ryan S. Holmqvist , Steven E. Strauss
IPC分类号： G06F13/00 , H04L29/06 , H04L29/08 , H04L29/10 , G01R31/08
CPC分类号： H04L67/04 , H04L69/22 , H04L69/32 , H04L69/323
摘要： A translation system and related method for use with a communications device having a physical layer system and a data link layer system with a media access control layer subsystem and coupleable to a communications network. In one embodiment, the translation system includes a generator that constructs a piggyback packet containing characteristics associated with the physical layer system. The translation system also includes a correlator, coupled to the generator, that receives the piggyback packet and extracts information about the physical layer system. The generator and correlator transmit and receive the piggyback packet without substantially modifying the media access control layer subsystem.
摘要翻译：一种用于具有物理层系统的通信设备和具有媒体访问控制层子系统并可与通信网络耦合的数据链路层系统的翻译系统和相关方法。在一个实施例中，翻译系统包括生成器，其构造包含与物理层系统相关联的特征的搭载分组。翻译系统还包括耦合到发生器的相关器，其接收捎带包并提取关于物理层系统的信息。发电机和相关器发送和接收捎带分组，而基本上不修改媒体访问控制层子系统。

10. 发明授权

US5224064A Transcendental function approximation apparatus and method 失效
标题翻译：传统函数近似装置和方法
公开(公告)号：US5224064A
公开(公告)日：1993-06-29
申请号：US728445
申请日：1991-07-11
申请人： Matthew R. Henry , Gregory M. Martin
发明人： Matthew R. Henry , Gregory M. Martin
IPC分类号： G06F1/02 , G06F1/035 , G06F7/548 , G06F17/17
CPC分类号： G06F1/0356
摘要： Transcendental function approximation using a regional approximation look-up table, offset lookup table, scaling shifter and interpolation adder/subtractor. Rapid fixed-point arithmetic calculations can be accomplished which approximate values of transcendental functions to a predetermined accuracy. An N bit argument is used to produce an N bit result allowing the placement of the radix point in the two numbers to be different. Different parts of the input argument are fed in parallel to the regional approximation look-up table and the offset lookup table. A scaling shifter converts the output of the offset lookup table and regional lookup table to a result usable by the interpolation adder/subtractor processor. The regional approximation lookup table also provides information to the interpolation processor which provides the N bit approximation.

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