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31. 发明授权

US6163045A Reduced parasitic leakage in semiconductor devices 有权
标题翻译：减少半导体器件中的寄生泄漏
公开(公告)号：US6163045A
公开(公告)日：2000-12-19
申请号：US215011
申请日：1998-12-17
申请人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
发明人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10829
摘要： A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.
摘要翻译：一种沟槽式电容器，其具有与该套环相邻的扩散区域以增加寄生MOSFET的栅极阈值电压。这使得能够使用更薄的套环，同时仍然实现可接受的泄漏。在一个实施例中，扩散区域是自对准的。

32. 发明授权

US5484738A Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits 失效
标题翻译：用于BiCMOS集成电路的氧化物半导体器件结构上形成硅的方法
公开(公告)号：US5484738A
公开(公告)日：1996-01-16
申请号：US396985
申请日：1995-03-01
申请人： Shao-Fu S. Chu , Chang-Ming Hsieh , Louis L. C. Hsu , Kyong-Min Kim , Shaw-Ning Mei
发明人： Shao-Fu S. Chu , Chang-Ming Hsieh , Louis L. C. Hsu , Kyong-Min Kim , Shaw-Ning Mei
IPC分类号： H01L21/76 , H01L21/02 , H01L21/762 , H01L21/8249 , H01L27/06 , H01L27/12 , H01L29/786 , H01L21/265
CPC分类号： H01L21/8249 , H01L21/76251 , H01L27/0623 , Y10S148/01 , Y10S148/011 , Y10S148/012 , Y10S148/05 , Y10S148/151
摘要： A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.
摘要翻译：首先形成在体硅晶片中的具有阶梯式隔离沟槽和子层互连的键合SOI晶片。在这些工艺步骤完成之后，在本体硅晶片的平坦化上表面上形成薄多晶硅层。然后将该薄多晶硅层结合到单独晶片的表面上的氧化物层，以形成键合的氧化硅结构。整个组件实际上是倒置的，并且本体硅晶片的下表面被移除到最深沟槽台阶的底部。在这种键合的SOI结构中，沟槽之间的区域是深的并且适合于双极器件制造，而沟槽台阶形成适于制造CMOS器件的浅区域。

33. 发明授权

US5341023A Novel vertical-gate CMOS compatible lateral bipolar transistor 失效
标题翻译：新型垂直门CMOS兼容横向双极晶体管
公开(公告)号：US5341023A
公开(公告)日：1994-08-23
申请号：US900881
申请日：1992-06-18
申请人： Chang-Ming Hsieh , Louis L. C. Hsu , Shaw-Ning Mei , Ronald W. Knepper , Lawrence F. Wagner, Jr.
发明人： Chang-Ming Hsieh , Louis L. C. Hsu , Shaw-Ning Mei , Ronald W. Knepper , Lawrence F. Wagner, Jr.
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/735 , H01L29/72
CPC分类号： H01L29/7317 , H01L27/0623 , H01L29/735
摘要： A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.
摘要翻译：横向双极晶体管在中心布置的发射极层的任一侧上具有非本征基极层，并且本征基极和集电极垂直于外部基极和集电极层取向。

34. 发明申请

US20120051166A1 SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD 失效
标题翻译：自修复集成电路和维修方法
公开(公告)号：US20120051166A1
公开(公告)日：2012-03-01
申请号：US13288472
申请日：2011-11-03
申请人： Louis L. C. Hsu , Rajiv V. Joshi , Zhijian J. Yang , Ping-Chuan Wang
发明人： Louis L. C. Hsu , Rajiv V. Joshi , Zhijian J. Yang , Ping-Chuan Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/04 , G11C7/12 , G11C11/412
摘要： A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.
摘要翻译：用于修复劣化场效应晶体管的方法包括场效应晶体管（FET）的源极和漏极之一的正偏置PN结以及FET的主体。电荷从衬底注入到栅极区域以中和栅极区域中的电荷。该方法适用于CMOS器件。公开了用于实施修理的维修电路。

35. 发明申请

US20090190413A1 SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD 有权
标题翻译：自修复集成电路和维修方法
公开(公告)号：US20090190413A1
公开(公告)日：2009-07-30
申请号：US12019240
申请日：2008-01-24
申请人： Louis L. C. Hsu , Rajiv V. Joshi , Zhijian J. Yang , Ping-Chuan Wang
发明人： Louis L. C. Hsu , Rajiv V. Joshi , Zhijian J. Yang , Ping-Chuan Wang
IPC分类号： G11C5/14 , H01L21/00
CPC分类号： G11C29/04 , G11C7/12 , G11C11/412
摘要： A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.
摘要翻译：用于修复劣化场效应晶体管的方法包括场效应晶体管（FET）的源极和漏极之一的正偏置PN结以及FET的主体。电荷从衬底注入到栅极区域以中和栅极区域中的电荷。该方法适用于CMOS器件。公开了用于实施修理的维修电路。

36. 发明授权

US07560310B2 Semiconductor constructions and semiconductor device fabrication methods 有权
标题翻译：半导体结构和半导体器件制造方法
公开(公告)号：US07560310B2
公开(公告)日：2009-07-14
申请号：US11965445
申请日：2007-12-27
申请人： Louis L. C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman
发明人： Louis L. C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman
IPC分类号： H01L21/00
CPC分类号： H01L23/3677 , H01L2924/0002 , H01L2924/10158 , Y10S438/928 , Y10S438/96 , Y10S438/977 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.
摘要翻译：一种制造半导体器件的方法包括蚀刻形成在半导体晶片的背面上的衬底，以在衬底中形成凹陷，并且在凹部中形成溅射膜，溅射膜包括具有热膨胀系数的第一材料（ CTE），其至少基本上等于衬底的CTE，以及具有大于衬底的热导率的导热性的第二材料。

37. 发明授权

US07460389B2 Write operations for phase-change-material memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US07460389B2
公开(公告)日：2008-12-02
申请号：US11193878
申请日：2005-07-29
申请人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： G11C13/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

38. 发明授权

US06278317B1 Charge pump system having multiple charging rates and corresponding method 有权
标题翻译：电荷泵系统具有多种充电率和相应的方法
公开(公告)号：US06278317B1
公开(公告)日：2001-08-21
申请号：US09430807
申请日：1999-10-29
申请人： Louis L. C. Hsu , Oliver Weinfurtner , Matthew R. Wordeman
发明人： Louis L. C. Hsu , Oliver Weinfurtner , Matthew R. Wordeman
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： A charge pump generator system and method is provided in which one or more charge pumps are operated at multiple charging rates depending upon the level reached by a voltage supply. The system includes a limiter which provides a control signal based upon the level of the voltage supply. The control signal selects the frequency of a multiple frequency oscillator coupled thereto. The selected frequency determines the charge transfer rate of a charge pump used to maintain the voltage supply.
摘要翻译：提供一种电荷泵发电机系统和方法，其中一个或多个电荷泵根据电压供应达到的电平以多种充电速率运行。该系统包括限幅器，其基于电压电平的电平提供控制信号。控制信号选择与其耦合的多频振荡器的频率。所选择的频率决定了用于维持电压供应的电荷泵的电荷转移速率。

39. 发明授权

US6049495A Auto-programmable current limiter to control current leakage due to bitline to wordline short 有权
标题翻译：自动可编程限流器，用于控制由于位线到字线短路引起的电流泄漏
公开(公告)号：US6049495A
公开(公告)日：2000-04-11
申请号：US243646
申请日：1999-02-03
申请人： Louis L. C. Hsu , Giuseppe La Rosa , Jack A. Mandelman
发明人： Louis L. C. Hsu , Giuseppe La Rosa , Jack A. Mandelman
IPC分类号： G11C11/404 , G11C29/02 , G11C29/50 , G11C7/00 , G11C16/04
CPC分类号： G11C29/025 , G11C11/404 , G11C29/02 , G11C29/50 , G11C11/401
摘要： A method and structure for disconnecting shorted bitlines from a dynamic random access memory circuit includes supplying a precharge voltage to equalization lines in the integrated circuit, supplying a negative voltage to wordlines in the integrated circuit, activating equalization devices connected to the bitlines and the equalization lines and maintaining the precharge voltage and the negative voltage until a short between one of the bitlines and one of the wordlines causes a corresponding equalization device of the equalization devices to have a permanently elevated threshold voltage.
摘要翻译：用于从动态随机存取存储器电路断开短路位线的方法和结构包括向集成电路中的均衡线提供预充电电压，向集成电路中的字线提供负电压，激活连接到位线和均衡线的均衡器件并且保持预充电电压和负电压，直到位线之一和字线之一之间的短路导致均衡装置的相应均衡装置具有永久升高的阈值电压。

40. 发明授权

US5528062A High-density DRAM structure on soi 失效
标题翻译：高密度DRAM结构在soi上
公开(公告)号：US5528062A
公开(公告)日：1996-06-18
申请号：US900041
申请日：1992-06-17
申请人： Chang-Ming Hsieh , Louis L. C. Hsu , Seiki Ogura
发明人： Chang-Ming Hsieh , Louis L. C. Hsu , Seiki Ogura
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10829 , H01L27/10823
摘要： A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.
摘要翻译：具有非常短的通道的高密度DRAM单元阵列，垂直栅极转移晶体管可以使用常规光刻工艺步骤制造。图1中示意性示出的常规四乘四DRAM阵列。 1a被重新布置到图1中示意性示出的共享门双位阵列。 1b。沟槽存储电容器和垂直FET晶体管与公共垂直栅极和公共衬底成对配置，允许位和衬底触点由相邻单元共享。

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