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1. 发明授权

US5981332A Reduced parasitic leakage in semiconductor devices 失效
公开(公告)号：US5981332A
公开(公告)日：1999-11-09
申请号：US940237
申请日：1997-09-30
申请人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
发明人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10829
摘要： A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.

2. 发明授权

US6163045A Reduced parasitic leakage in semiconductor devices 有权
标题翻译：减少半导体器件中的寄生泄漏
公开(公告)号：US6163045A
公开(公告)日：2000-12-19
申请号：US215011
申请日：1998-12-17
申请人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
发明人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10829
摘要： A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.
摘要翻译：一种沟槽式电容器，其具有与该套环相邻的扩散区域以增加寄生MOSFET的栅极阈值电压。这使得能够使用更薄的套环，同时仍然实现可接受的泄漏。在一个实施例中，扩散区域是自对准的。

3. 发明授权

US06759291B2 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06759291B2
公开(公告)日：2004-07-06
申请号：US10045499
申请日：2002-01-14
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

4. 发明授权

US06369419B1 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06369419B1
公开(公告)日：2002-04-09
申请号：US09603657
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L2994
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

5. 发明授权

US5559050A P-MOSFETS with enhanced anomalous narrow channel effect 失效
标题翻译：具有增强的异常窄通道效应的P-MOSFET
公开(公告)号：US5559050A
公开(公告)日：1996-09-24
申请号：US269857
申请日：1994-06-30
申请人： Johann Alsmeier , Wayne F. Ellis , Jack A. Mandelman , Hing Wong
发明人： Johann Alsmeier , Wayne F. Ellis , Jack A. Mandelman , Hing Wong
IPC分类号： H01L21/265 , H01L21/322 , H01L27/092 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/1095 , H01L27/0921 , H01L29/0642 , H01L29/1033 , H01L29/7838
摘要： An anomalous threshold voltage dependence on channel width measured on 0.25 .mu.m ground rule generation trench-isolated buried-channel p-MOSFETs is used to enhance circuit performance. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in V.sub.t for widths narrower than 0.4 .mu.m. Modeling shows that a "boron puddle" is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step, which imposes a penalty on the off-current of narrow devices. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device.
摘要翻译：在0.25微米接地规则生成沟槽隔离埋沟p-MOSFET上测量的通道宽度的异常阈值电压依赖性用于增强电路性能。随着沟道宽度的减小，阈值电压的幅度首先在宽度窄于0.4μm的Vt预期的急剧上升之前降低。建模表明，在栅极氧化步骤期间，由于瞬态增强扩散（TED）的结果，在沟槽界限边缘附近产生“硼熔池”，这对狭窄器件的截止电流造成了惩罚。 TED由深磷植入物产生的间隙控制，用于闭锁抑制，向器件的沟槽侧壁和顶表面扩散。

6. 发明授权

US08824183B2 Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof 有权
标题翻译：具有具有垂直位线的读/写元件的3D阵列的非易失性存储器及其选择装置及其方法
公开(公告)号：US08824183B2
公开(公告)日：2014-09-02
申请号：US13323780
申请日：2011-12-12
申请人： George Samachisa , Johann Alsmeier
发明人： George Samachisa , Johann Alsmeier
IPC分类号： G11C5/02
CPC分类号： H01L27/11551 , G11C5/025 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2213/71 , H01L21/306 , H01L21/76224 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/1226 , H01L45/1273 , H01L45/144 , H01L45/146 , H01L45/149 , H01L45/1616
摘要： A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate.
摘要翻译：形成三维存储器作为形成在位于半导体衬底上方不同距离的多层平面上的存储元件的阵列。存储元件响应于在其上施加的电压差而可逆地改变电导级。三维阵列包括通过多层平面的作为局部垂直位线的柱线的二维阵列，每个平面上的字线阵列被用于访问存储器元件。在具有中间柱选择层的CMOS衬底上形成三维存储器。柱选择层形成有多个柱选择器件，其是形成在CMOS外部的开关晶体管，用于将所选择的行列切换到衬底上相应的金属线。

7. 发明授权

US08614126B1 Method of making a three-dimensional memory array with etch stop 有权
标题翻译：制造具有蚀刻停止的三维存储阵列的方法
公开(公告)号：US08614126B1
公开(公告)日：2013-12-24
申请号：US13586413
申请日：2012-08-15
申请人： Yao-Sheng Lee , Johann Alsmeier
发明人： Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L21/8238
CPC分类号： H01L27/11551 , H01L21/764 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.
摘要翻译：一种包括衬底和半导体沟道的三维存储器件。半导体通道的至少一个端部基本上垂直于衬底的主表面延伸。该器件还包括位于半导体通道附近的至少一个电荷存储区域以及具有基本上平行于衬底的主表面延伸的条带形状的多个控制栅极电极。多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于位于衬底的主表面上方且低于第一器件电平的第二器件电平的第二控制栅电极。该器件还包括位于衬底和多个控制栅电极之间的蚀刻停止层。

8. 发明授权

US08330208B2 Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof 有权
标题翻译：超高密度单片三维垂直NAND串存储器件及其制造方法
公开(公告)号：US08330208B2
公开(公告)日：2012-12-11
申请号：US13451009
申请日：2012-04-19
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

9. 发明申请

US20120256247A1 3D Vertical NAND and Method of Making Thereof by Front and Back Side Processing 有权
标题翻译： 3D垂直NAND及其前后处理方法
公开(公告)号：US20120256247A1
公开(公告)日：2012-10-11
申请号：US13083775
申请日：2011-04-11
申请人： Johann Alsmeier
发明人： Johann Alsmeier
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11556 , H01L21/764 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Monolithic three dimensional NAND strings and methods of making. The method includes both front side and back side processing. Using the combination of front side and back side processing, a NAND string can be formed that includes an air gap between the floating gates in the NAND string. The NAND string may be formed with a single vertical channel. Alternatively, the NAND string may have a U shape with two vertical channels connected with a horizontal channel.
摘要翻译：单片三维NAND串和制作方法。该方法包括正面和背面处理。使用前侧和背面处理的组合，可以形成NAND串，其包括NAND串中的浮动栅极之间的气隙。 NAND串可以形成有单个垂直通道。或者，NAND串可以具有U形，其中两个垂直通道与水平通道连接。

10. 发明申请

US20120220088A1 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 有权
公开(公告)号：US20120220088A1
公开(公告)日：2012-08-30
申请号：US13467245
申请日：2012-05-09
申请人： Johann Alsmeier
发明人： Johann Alsmeier
IPC分类号： H01L21/8247
CPC分类号： H01L29/7889 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

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