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31. 发明授权

US06667243B1 Etch damage repair with thermal annealing 有权
标题翻译：蚀刻损伤修复与热退火
公开(公告)号：US06667243B1
公开(公告)日：2003-12-23
申请号：US10222248
申请日：2002-08-16
申请人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal , Jeffrey A. Shields , Yider Wu
发明人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal , Jeffrey A. Shields , Yider Wu
IPC分类号： H01L21302
CPC分类号： H01L21/02071 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L29/6659 , Y10S438/906 , Y10S438/94
摘要： A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.
摘要翻译：半导体器件的制造方法根据光致抗蚀剂掩模蚀刻衬底上的特征。通过等离子体蚀刻去除光致抗蚀剂掩模。进行激光热退火以蒸发在光刻胶掩模剥离期间产生的聚合物残余物，并修复对基材的损伤。

32. 发明授权

US06730564B1 Salicided gate for virtual ground arrays 有权
标题翻译：用于虚拟地面阵列的闸门
公开(公告)号：US06730564B1
公开(公告)日：2004-05-04
申请号：US10217821
申请日：2002-08-12
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , Y10S438/954
摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
摘要翻译：本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。未图案化的层保护字线之间的基板不会变成水银。本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

33. 发明授权

US06630384B1 Method of fabricating double densed core gates in sonos flash memory 有权
标题翻译：在sonos闪存中制造双激光核心门的方法
公开(公告)号：US06630384B1
公开(公告)日：2003-10-07
申请号：US09971483
申请日：2001-10-05
申请人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
发明人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.
摘要翻译：本发明的一个方面涉及一种形成非易失性半导体存储器件的方法，包括在衬底上形成电荷俘获电介质，所述衬底具有芯区域和外围区域; 在芯区域中的电荷俘获电介质上形成第一组存储单元栅极; 在所述第一组存储单元栅极周围形成保形绝缘材料层; 以及在所述核心区域中形成第二组存储器单元栅极，其中所述第二组存储单元栅极的每个存储单元栅极与所述第一组存储单元栅极的至少一个存储单元栅极相邻，第一组存储单元栅极与第二组存储单元栅极的至少一个存储单元栅极相邻，并且保形绝缘材料层位于每个相邻的存储单元栅极之间。

34. 发明授权

US06232630B1 Light floating gate doping to improve tunnel oxide reliability 有权
标题翻译：光浮栅掺杂提高隧道氧化可靠性
公开(公告)号：US06232630B1
公开(公告)日：2001-05-15
申请号：US09348583
申请日：1999-07-07
申请人： Mark T. Ramsbey , Tuan Pham , Yu Sun , Kenneth Wo-Wai Au , David H. Chi
发明人： Mark T. Ramsbey , Tuan Pham , Yu Sun , Kenneth Wo-Wai Au , David H. Chi
IPC分类号： H01L2972
CPC分类号： H01L29/42324
摘要： The reliability of a tunnel oxide is improved by light doping of the floating gate, as with phosphorous or arsenic atoms. Doping can be implemented by ion implantation or by in situ deposition. The relatively low dopant concentration further enhances charge retention on the floating gate.
摘要翻译：隧道氧化物的可靠性通过浮栅的轻掺杂而改善，如同磷或砷原子一样。掺杂可以通过离子注入或原位沉积来实现。相对低的掺杂剂浓度进一步增强了浮栅上的电荷保持。

35. 发明授权

US08673716B2 Memory manufacturing process with bitline isolation 有权
标题翻译：内存制造过程采用位线隔离
公开(公告)号：US08673716B2
公开(公告)日：2014-03-18
申请号：US10118732
申请日：2002-04-08
申请人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
发明人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.
摘要翻译：集成电路的制造方法具有具有芯区域和周边区域的半导体基板。在芯区域中沉积电荷捕获电介质层，并且在周边区域中沉积栅极电介质层。位线在芯区域中的半导体衬底中而不是在周边区域中形成。在芯区域而不是周边区域中形成并注入掺杂剂的字线栅层。形成了一条字和门。源极/漏极结在栅极周围的半导体衬底中注入掺杂剂，栅极注入栅极掺杂注入在外围区域而不在核心区域。

36. 发明授权

US06235584B1 Method and system for reducing short channel effects in a memory device 有权
标题翻译：用于减少存储器件中的短通道效应的方法和系统
公开(公告)号：US06235584B1
公开(公告)日：2001-05-22
申请号：US09412544
申请日：1999-10-05
申请人： Yu Sun , Mark T. Ramsbey , Tommy Hsiao
发明人： Yu Sun , Mark T. Ramsbey , Tommy Hsiao
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/66659 , H01L29/7835
摘要： A method and system for providing a semiconductor memory device is disclosed. The method and system include providing a plurality of gate stacks above a substrate. Each of the plurality of gate stacks includes a first edge and a second edge. The method and system also include providing a source implant adjacent to the first edge of each of the plurality of gate stacks and driving the source implant under the first edge of each of the plurality of gate stacks. The method and system also include providing a first spacer and a second spacer for each of the plurality of gate stacks. The first and second spacers are disposed along the first and second edges, respectively, of each of the plurality of gate stacks. The method and system also include providing a drain implant after source implant is driven under the first edge and after the first and second spacers are provided. The drain implant is in the substrate adjacent to the second spacer.
摘要翻译：公开了一种用于提供半导体存储器件的方法和系统。该方法和系统包括在衬底上方提供多个栅叠层。多个栅极堆叠中的每一个包括第一边缘和第二边缘。该方法和系统还包括提供与多个栅极堆叠中的每一个的第一边缘相邻的源极注入，并且在多个栅极堆叠中的每一个的第一边缘的下方驱动源极注入。该方法和系统还包括为多个栅极堆叠中的每一个提供第一间隔物和第二间隔物。第一和第二间隔物分别沿着多个栅极堆叠中的每一个的第一和第二边缘设置。所述方法和系统还包括在源植入物在第一边缘下被驱动并且在提供第一和第二间隔物之后提供漏极注入。漏极注入在与第二间隔物相邻的衬底中。

37. 发明授权

US06200857B1 Method of manufacturing a semiconductor device without arc loss in peripheral circuit region 有权
标题翻译：在外围电路区域中制造没有电弧损耗的半导体器件的方法
公开(公告)号：US06200857B1
公开(公告)日：2001-03-13
申请号：US09417132
申请日：1999-10-13
申请人： Tommy C. Hsiao , Mark T. Ramsbey , Yu Sun
发明人： Tommy C. Hsiao , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/11541 , Y10S438/981
摘要： Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.
摘要翻译：半导体器件的外围电路区域中的栅电极结构的改进的尺寸精度通过在图案化和离子注入期间避免与芯存储器单元区域中的多个掩模相关联的光致抗蚀剂剥离期间的ARC损耗来实现。实施例包括初始蚀刻以在外围电路区域中形成栅电极结构。随后，通过蚀刻堆叠的栅极电极结构和离子注入来进行核心存储单元区域中的处理，以形成具有光刻胶层的伴随剥离的源极/漏极。

38. 发明授权

US6160317A Method of spacer formation and source protection after self-aligned source formed and a device provided by such a method 有权
标题翻译：自对准源形成后的间隔物形成和源保护方法以及通过这种方法提供的器件
公开(公告)号：US6160317A
公开(公告)日：2000-12-12
申请号：US336057
申请日：1999-06-18
申请人： Yu Sun , Chi Chang , Mark T. Ramsbey
发明人： Yu Sun , Chi Chang , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/088
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.
摘要翻译：本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

39. 发明授权

US06787840B1 Nitridated tunnel oxide barriers for flash memory technology circuitry 失效
标题翻译：用于闪存技术电路的氮化隧道氧化物屏障
公开(公告)号：US06787840B1
公开(公告)日：2004-09-07
申请号：US09492931
申请日：2000-01-27
申请人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer. Periphery stacks have hate oxide layers of different thicknesses.
摘要翻译：具有多个闪存器件的半导体芯片，周边区域中的浅沟槽隔离以及芯区域中的LOCOS隔离。首先使用硬掩模来创建浅沟槽隔离。然后创建LOCOS隔离。随后的蚀刻用于去除桁条。闪存能够使用浅沟槽隔离来限制侵占。闪存也可以具有氮化的隧道氧化物阻挡层。使用硬掩模来防止栅极氧化物层的氮化物污染。外围堆叠具有不同厚度的恶性氧化物层。

40. 发明授权

US06605511B2 Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation 失效
标题翻译：形成用于闪存技术电路的氮化隧道氧化物屏障的方法和STI和LOCOS隔离
公开(公告)号：US06605511B2
公开(公告)日：2003-08-12
申请号：US10295738
申请日：2002-11-15
申请人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L218234
CPC分类号： H01L21/76202 , H01L21/76224 , H01L27/1052 , Y10S438/981
摘要： A method of fabricating an improved flash memory device, having shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided, by first creating the shallow trench isolation using a hard mask; then creating the LOCOS isolation; and subsequently etching to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.
摘要翻译：提供了一种通过首先使用硬掩模创建浅沟槽隔离来制造在外围区域中具有浅沟槽隔离和芯区域中的LOCOS隔离的改进的闪速存储器件的方法; 然后创建LOCOS隔离; 并随后蚀刻以除去桁条。闪存能够使用浅沟槽隔离来限制侵占。闪存也可以具有氮化隧道氧化物层。使用硬掩模来防止栅极氧化物层的氮化物污染。

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