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31. 发明授权

US08379665B2 Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system 有权
标题翻译：用于光纤通道仲裁环路系统中多目标桥/路由器的接入公平性的装置和方法
公开(公告)号：US08379665B2
公开(公告)日：2013-02-19
申请号：US12475694
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
发明人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
IPC分类号： H04J3/02
CPC分类号： H04L12/427
摘要： Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.
摘要翻译：装置和方法通过桥接装置改善了对光纤通道仲裁环（FC-AL）通信介质的公平访问。增强型桥接器件在当前打开的访问窗口中为通过桥接设备耦合到FC-AL通信介质的所有当前请求设备提供公平的访问。因此，当在开放访问窗口中存在同时请求时，环路上的所有设备无论是直接耦合还是通过桥接设备都可以确保公平地访问环路。

32. 发明授权

US5404535A Apparatus and method for providing more effective reiterations of processing task requests in a multiprocessor system 失效
标题翻译：用于在多处理器系统中提供更有效重复处理任务请求的装置和方法
公开(公告)号：US5404535A
公开(公告)日：1995-04-04
申请号：US781524
申请日：1991-10-22
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F9/46 , G06F13/24 , G06F13/26 , G06F15/16 , G06F15/17 , G06F15/177
CPC分类号： G06F13/24 , G06F13/26 , G06F15/17
摘要： A multiprocessor computer system having a first processor having a first interrupt mechanism for generating interrupt requests, a second processor having a second interrupt mechanism, and a system bus for communicating interrupt requests from the first processor to the second processor. The second interrupt mechanism is responsive to an interrupt request by generating an acknowledge response on the system bus when the second processor accepts the interrupt request and generating a not acknowledge response on the system bus when the second processor contains a previous and pending interrupt request of higher level and refuses the interrupt request. The second interrupt mechanism is responsive to the completion of servicing of an interrupt request by the second processor by placing on the system bus an interrupt completed command, which includes an address identifying the second processor and a code indicating that the second processor has completing servicing an interrupt request. The first processor includes an interrupt retry means, which includes a refused interrupt register means responsive to a not acknowledge response from the second processor in response to an interrupt requested from the first processor for storing the channel number of the second processor, and level monitor logic connected from the system bus.
摘要翻译：一种具有第一处理器的多处理器计算机系统，具有用于产生中断请求的第一中断机制，具有第二中断机制的第二处理器和用于将来自第一处理器的中断请求传送到第二处理器的系统总线。第二中断机制响应于中断请求，当第二处理器接收到中断请求并且当第二处理器包含较高的先前和未决中断请求时，在系统总线上产生不确认响应时，通过在系统总线上产生确认响应级别并拒绝中断请求。第二中断机制响应于由第二处理器完成对中断请求的完成，通过在系统总线上放置一个中断完成命令，该命令包括标识第二处理器的地址和指示第二处理器完成服务的代码中断请求。第一处理器包括中断重试装置，其包括响应于从第一处理器请求的用于存储第二处理器的信道号的中断响应来自第二处理器的不确认响应的拒绝中断寄存器装置，以及级别监视器逻辑从系统总线连接。

33. 发明授权

US5379378A Data processing system having a bus command generated by one subsystem on behalf of another subsystem 失效
标题翻译：数据处理系统具有由一个子系统代表另一子系统产生的总线命令
公开(公告)号：US5379378A
公开(公告)日：1995-01-03
申请号：US773752
申请日：1991-10-10
申请人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
发明人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
IPC分类号： G06F13/362 , G06F13/26 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4243
摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.
摘要翻译：数据处理系统包括系统管理单元，多个中央子系统，主存储器和多个共同连接到系统总线的外围子系统。任何子系统可以生成包括指定目的地子系统的第一字段的命令，指定目的地子系统要执行的操作的第二字段。如果需要响应，则生成初始命令的子系统可以指定用于接收响应命令的第三子系统。

34. 发明授权

US5283870A Method and apparatus for avoiding processor deadly embrace in a multiprocessor system 失效
标题翻译：用于在多处理器系统中避免处理器致命包围的方法和装置
公开(公告)号：US5283870A
公开(公告)日：1994-02-01
申请号：US771296
申请日：1991-10-04
申请人： Thomas F. Joyce , James W. Keeley
发明人： Thomas F. Joyce , James W. Keeley
IPC分类号： G06F9/46 , G06F15/167 , G06F13/14
CPC分类号： G06F9/524 , G06F15/167
摘要： A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.
摘要翻译：多处理器系统包括许多系统处理器，其紧密耦合到系统总线以共享主或系统存储器以及还紧密耦合到系统总线的多个板载存储器处理器。每个处理器都有一个高性能微处理器，通过微处理器的本地总线紧密耦合到板载或本地存储器。使用内存锁定协议访问系统内存，而本地内存可通过总线锁定协议访问。每个板上存储器处理器包括锁机构，其能够处理针对其本地存储器的存储器锁定命令，该存储器锁定命令经由系统总线从任何其他处理器接收并用于向系统存储器发出存储器锁定命令。

35. 发明授权

US5210757A Method and apparatus for performing health tests of units of a data processing system 失效
标题翻译：用于对数据处理系统的单元执行健康测试的方法和装置
公开(公告)号：US5210757A
公开(公告)日：1993-05-11
申请号：US593408
申请日：1990-10-05
申请人： George J. Barlow , Richard C. Zelley , James W. Keeley
发明人： George J. Barlow , Richard C. Zelley , James W. Keeley
IPC分类号： G06F11/00 , G06F11/22 , G06F11/273
CPC分类号： G06F11/22 , G06F11/2736 , G06F11/0757
摘要： A means for ascertaining the health, or basic operational status, of a system unit. A "health check" provides an indication of either "yes", the system unit is operational, or "no", the system unit is either inoperative or there is a question as to whether the system is operational. The test is performed by requesting that the system unit perform a high priority "short" operation and noting the response provided to the request; the actual execution of the request is unimportant and it is the response of the unit under test to the receipt of the request for a bus operation that is the actual indicator of the status of the unit being tested. The requested operation is not directed at the unit whose operational status is to be determined, but instead at a bus interface unit which performs bus operations for the unit to be tested and whose responses to requests for bus operations are effected by the operational status of the unit that is to be tested. The operation is not directed at an actual element in the bus interface unit, but at a phantom, or nonexistent, element.
摘要翻译：一种用于确定系统单元的健康或基本操作状态的方法。 “健康检查”提供“是”，系统单元运行或“否”的指示，系统单元不工作或者是否存在系统是否可操作的问题。通过请求系统单元执行高优先级“短”操作并注意提供给请求的响应来执行测试; 请求的实际执行不重要，并且是接收到总线操作请求的被测单元的响应，该总线操作是正在测试的单元的状态的实际指示符。所请求的操作不是针对要确定其操作状态的单元，而是指向执行待测单元的总线操作的总线接口单元，并且其对总线操作请求的响应由要测试的单位该操作不是针对总线接口单元中的实际元件，而是以幻像或不存在的元素。

36. 发明授权

US4910666A Apparatus for loading and verifying a control store memory of a central subsystem 失效
标题翻译：用于加载和验证中央子系统的控制存储器的装置
公开(公告)号：US4910666A
公开(公告)日：1990-03-20
申请号：US943984
申请日：1986-12-18
申请人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
发明人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
IPC分类号： G06F9/445 , G06F9/22 , G06F9/24
CPC分类号： G06F9/24
摘要： A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

37. 发明授权

US4799222A Address transform method and apparatus for transferring addresses 失效
标题翻译：用于传送地址的地址变换方法和装置
公开(公告)号：US4799222A
公开(公告)日：1989-01-17
申请号：US001124
申请日：1987-01-07
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/10 , G06F12/08 , G06F12/10 , G06F12/16
CPC分类号： G06F11/10 , G06F12/0802
摘要： An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.
摘要翻译：从多个源传送地址的地址路径包括递增电路。地址包括多个地址位和完整性位。地址位应用于递增电路，而完整性位并行应用于可编程逻辑器件（PLD）。当地址正在根据需要被传送或递增时，PLD独立地产生多个变换位，定义预测为改变状态的地址位数的特性。此后，变换位用于变换用于递增地址的传送的地址完整性位。逻辑地组合递增地址，变换位和完整性位，以验证地址是否被传送和/或递增而没有错误。

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