专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08379665B2 Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system 有权
标题翻译：用于光纤通道仲裁环路系统中多目标桥/路由器的接入公平性的装置和方法
公开(公告)号：US08379665B2
公开(公告)日：2013-02-19
申请号：US12475694
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
发明人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
IPC分类号： H04J3/02
CPC分类号： H04L12/427
摘要： Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.
摘要翻译：装置和方法通过桥接装置改善了对光纤通道仲裁环（FC-AL）通信介质的公平访问。增强型桥接器件在当前打开的访问窗口中为通过桥接设备耦合到FC-AL通信介质的所有当前请求设备提供公平的访问。因此，当在开放访问窗口中存在同时请求时，环路上的所有设备无论是直接耦合还是通过桥接设备都可以确保公平地访问环路。

2. 发明申请

US20100303084A1 APPARATUS AND METHODS FOR ACCESS FAIRNESS FOR A MULTIPLE TARGET BRIDGE/ROUTER IN A FIBRE CHANNEL ARBITRATED LOOP SYSTEM 有权
标题翻译：用于光纤通道仲裁环路系统中的多个目标桥/路由器的访问方法的装置和方法
公开(公告)号：US20100303084A1
公开(公告)日：2010-12-02
申请号：US12475694
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
发明人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
IPC分类号： H04L12/56
CPC分类号： H04L12/427
摘要： Apparatus and methods improved fair access to a Fibre Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.
摘要翻译：装置和方法通过桥接装置改善了对光纤通道仲裁环（FC-AL）通信介质的公平访问。增强型桥接器件在当前打开的访问窗口中为通过桥接设备耦合到FC-AL通信介质的所有当前请求设备提供公平的访问。因此，当在开放访问窗口中存在同时请求时，环路上的所有设备无论是直接耦合还是通过桥接设备都可以确保公平地访问环路。

3. 发明授权

US08116330B2 Bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loop 失效
标题翻译：用于将多个非光纤信道设备耦合到光纤信道仲裁环路的桥接设备和方法
公开(公告)号：US08116330B2
公开(公告)日：2012-02-14
申请号：US12475838
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Andrew Hyonil Chong
发明人： James W. Keeley , Douglas E. Sanders , Andrew Hyonil Chong
IPC分类号： H04L12/56
CPC分类号： G06F13/404
摘要： Apparatus and methods for an enhanced bridge device for coupling multiple non-Fiber Channel storage devices to a Fiber Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.
摘要翻译：用于将多个非光纤通道存储设备耦合到光纤通道仲裁环（FC-AL）通信介质的增强桥接设备的装置和方法。其特征和方面提供了用于处理环路端口旁路（LPB）和环路端口使能（LPE）原语序列的FC-AL增强电路，寻址到与桥耦合的存储设备相关联的任何目标仲裁环物理地址（T-ALPA）而不考虑由桥接设备处理并与与桥接设备耦合的其他存储设备相关联的其他T-ALPA的当前旁路/非旁路状态。

4. 发明申请

US20100303085A1 BRIDGE APPARATUS AND METHODS FOR COUPLING MULTIPLE NON-FIBRE CHANNEL DEVICES TO A FIBRE CHANNEL ARBITRATED LOOP 失效
标题翻译：用于将多个非光纤通道器件耦合到光纤通道仲裁环路的桥接器件和方法
公开(公告)号：US20100303085A1
公开(公告)日：2010-12-02
申请号：US12475838
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Andrew Hyonil Chong
发明人： James W. Keeley , Douglas E. Sanders , Andrew Hyonil Chong
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： G06F13/404
摘要： Apparatus and methods for an enhanced bridge device for coupling multiple non-Fibre Channel storage devices to a Fibre Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.
摘要翻译：用于将多个非光纤通道存储设备耦合到光纤通道仲裁环（FC-AL）通信介质的增强桥接设备的装置和方法。其特征和方面提供了用于处理环路端口旁路（LPB）和环路端口使能（LPE）原语序列的FC-AL增强电路，寻址到与桥耦合的存储设备相关联的任何目标仲裁环物理地址（T-ALPA）而不考虑由桥接设备处理并与与桥接设备耦合的其他存储设备相关联的其他T-ALPA的当前旁路/非旁路状态。

5. 发明授权

US5226150A Apparatus for suppressing an error report from an address for which an error has already been reported 失效
标题翻译：用于从已经报告了错误的地址抑制错误报告的装置
公开(公告)号：US5226150A
公开(公告)日：1993-07-06
申请号：US591196
申请日：1990-10-01
申请人： Michael A. Callander , Linda Chao , Douglas E. Sanders
发明人： Michael A. Callander , Linda Chao , Douglas E. Sanders
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1064 , G06F11/00
摘要： A write-back cache memory system is disclosed which includes a source of a sequence of memory addresses and a tag store coupled to the source of addresses and accessed by an index portion of said addresses, which produces information relating to the addresses. The write-back cache memory system also includes an error detector for detecting an error in the tag store information. Circuitry is included for reporting an error and saving the index which caused the error if an error is detected but no error has been previously detected. Comparing circuitry is included for comparing the index causing the current error to the previously saved address if an error is detected and an error has been previously detected; and if the address is not the same, then reporting a fatal error; otherwise, if the index is the same, then not reporting a fatal error.
摘要翻译：公开了一种回写式高速缓冲存储器系统，其包括存储器地址序列的源和耦合到地址源并由所述地址的索引部分访问的标签存储器，其产生与地址有关的信息。回写式高速缓冲存储器系统还包括用于检测标签存储信息中的错误的错误检测器。包括电路报告错误，并保存导致错误的索引，如果检测到错误，但没有检测到错误。包括比较电路，用于比较导致当前错误的索引与先前保存的地址，如果检测到错误并且先前检测到错误; 如果地址不一样，则报告一个致命错误; 否则，如果索引相同，则不报告致命错误。

6. 发明授权

US5006980A Pipelined digital CPU with deadlock resolution 失效
标题翻译：流水线数字CPU，具有死锁分辨率
公开(公告)号：US5006980A
公开(公告)日：1991-04-09
申请号：US222008
申请日：1988-07-20
申请人： Douglas E. Sanders , George M. Uhler , John F. Brown, III
发明人： Douglas E. Sanders , George M. Uhler , John F. Brown, III
IPC分类号： G06F9/28 , G06F9/38
CPC分类号： G06F9/3889 , G06F9/28 , G06F9/3824 , G06F9/3867
摘要： A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruction are needed, but the earlier instruction is not producing the memory request for the operands because the pipeline is stalled; this results in a deadlock. Using separate micro-pipelines, the earlier instruction is advanced independently of the rest of the pipeline, in the case of a deadlock, so that the operands for the later instruction are provided and the deadlock is broken.
摘要翻译：流水线CPU为执行单元和存储器管理单元采用单独的微指令流水线。在两个连续的指令中存在数据依赖关系时，流水线CPU可能会发生死锁。如果需要较早的指令提取的操作数，则后一条指令可能会停止流水线，但由于管道停滞，较早的指令不会产生操作数的存储器请求; 这会导致僵局。使用单独的微管道，在死锁的情况下，先前的指令独立于流水线的其余部分被提前，以便提供后续指令的操作数，并且死锁被破坏。

7. 发明授权

US5119483A Application of state silos for recovery from memory management exceptions 失效
标题翻译：从内存管理异常中应用状态孤岛进行恢复
公开(公告)号：US5119483A
公开(公告)日：1992-06-02
申请号：US221944
申请日：1988-07-20
申请人： William C. Madden , Douglas E. Sanders , G. Michael Uhler , William R. Wheeler
发明人： William C. Madden , Douglas E. Sanders , G. Michael Uhler , William R. Wheeler
IPC分类号： G06F9/26 , G06F9/30 , G06F9/38 , G06F12/10
CPC分类号： G06F9/3867 , G06F9/26 , G06F9/30149 , G06F9/3863 , G06F12/10 , Y10S707/99939
摘要： To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information. A microsequencer issues a series of microinstructions for each specifier or operation having been decoded, and also issues a series of microinstructions in a fault routine when a fault occurs. The microsequencer is also provided with a state silo so that the normal sequence of microinstruction execution is resumed when the fault is corrected.
摘要翻译：为了减少纠正故障所需的处理时间，流水线处理器的指令解码段和第一执行段被提供有在正常指令执行期间操作的“状态仓”以保存足够量的状态信息以立即重启指令解码器段和第一执行段，通过重新加载已经存储在状态列表中的状态信息。例如，状态孤岛包括由校正故障期间被禁止的公共时钟信号计时的寄存器队列。当故障被纠正时，多路复用器从相应流水线段使用的筒仓中选择状态信息。在优选实施例中，指令解码器段将可变长度宏指令解码为操作数说明符和在指定符上执行的操作。当新的操作数说明符或操作被解码时，第一执行段接收控制信息，否则保持先前接收到的控制信息。微定序器为每个说明符或操作已经解码了一系列微指令，并且在出现故障时也会在故障程序中发出一系列微指令。微定序器还设置有状态仓，使得当故障被校正时，微指令执行的正常序列被恢复。

8. 发明授权

US5557622A Method and apparatus for parity generation 失效
标题翻译：奇偶校验生成的方法和装置
公开(公告)号：US5557622A
公开(公告)日：1996-09-17
申请号：US518
申请日：1993-01-04
申请人： Soha M. N. Hassoun , Douglas E. Sanders
发明人： Soha M. N. Hassoun , Douglas E. Sanders
IPC分类号： G06F11/10 , H03M13/09 , H03M13/00
CPC分类号： G06F11/1064 , H03M13/09 , H03M13/098 , H03M13/6502
摘要： A parity generator for multibit binary data in which only a subset of bits change at one time includes a circuit for determining whether the number of bits in the subset to be changed is odd or even. A toggle signal generator generates a toggle signal only if the number of bits to be changed is odd. A toggling circuit selectively changes the level of the parity bit in response to the toggle signal.
摘要翻译：其中仅一位的子集一次改变的多位二进制数据的奇偶校验生成器包括用于确定要改变的子集中的比特数是奇数还是偶数的电路。只有当要更改的位数为奇数时，触发信号发生器才产生触发信号。切换电路响应于触发信号选择性地改变奇偶校验位的电平。

9. 发明授权

US5276852A Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions 失效
标题翻译：用于在回写高速缓存事务期间控制由多个处理器组件使用的处理器总线的方法和装置
公开(公告)号：US5276852A
公开(公告)日：1994-01-04
申请号：US32814
申请日：1993-03-15
申请人： Michael A. Callander , Douglas E. Sanders
发明人： Michael A. Callander , Douglas E. Sanders
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831
摘要： A CPU module has a processor, cache memory, cache controller, and system interface attached to a processor bus. The system interface is attached to a system bus shared by memory, I/O, and other CPU modules. The cache controller requests control of the processor bus from the processor, and grants control to the system interface. The system interface uses the processor bus to store fill data obtained from memory into the cache in response to a read miss. The system interface also monitors system bus traffic and forwards the addresses of cache blocks to be invalidated to the cache controller over an invalidate bus. The cache controller requests control of the processor bus during a read miss to perform invalidates and writebacks. The processor grants control to the cache controller before the read miss completes, enabling the cache controller to proceed, and then re-issues the read. A protocol between the cache controller and the system interface ensures that cache fills, invalidates, and writebacks are done in the correct order to maintain data coherency. As part of this protocol, the cache controller decides when the system interface may proceed with a fill, and grants the processor bus to the system interface accordingly.
摘要翻译： CPU模块具有连接到处理器总线的处理器，高速缓冲存储器，高速缓存控制器和系统接口。系统接口连接到由内存，I / O和其他CPU模块共享的系统总线。缓存控制器从处理器请求对处理器总线的控制，并且向系统接口授予控制权。系统接口使用处理器总线来响应于读取缺失而将从存储器获得的填充数据存储到高速缓存中。系统接口还监视系统总线流量，并通过无效总线将要无效的缓存块的地址转发到高速缓存控制器。缓存控制器在读取未命中时请求对处理器总线的控制，以执行无效和回写。在读取未命中完成之前，处理器向高速缓存控制器授予控制权，使高速缓存控制器继续进行，然后重新发布读取。高速缓存控制器和系统接口之间的协议确保缓存填充，无效和回写以正确的顺序完成，以保持数据一致性。作为该协议的一部分，高速缓存控制器决定系统接口何时进行填充，并相应地将处理器总线授予系统接口。

10. 发明授权

US5193163A Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol 失效
标题翻译：双层协议用于多组件总线拥有，并在多处理器缓存中实现回写协议
公开(公告)号：US5193163A
公开(公告)日：1993-03-09
申请号：US591197
申请日：1990-10-01
申请人： Douglas E. Sanders , Michael A. Callander
发明人： Douglas E. Sanders , Michael A. Callander
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831
摘要： A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately available for processing when the cache controller is otherwise idle. The second part of the queue is contained within a system interface to ensure that the system interface can detect and respond to more system transactions before the first invalidate request has been processed and to enable the system interface to be immediately aware if the entire queue is full.
摘要翻译：一种用于监视系统总线上用于无效请求的事务的方法和装置，包括用于存储被分成两部分的无效请求的队列。队列的第一部分包含在缓存控制器中，以确保当缓存控制器否则空闲时，无效请求立即可用于处理。队列的第二部分包含在系统接口中，以确保系统接口可以在处理第一个无效请求之前检测并响应更多的系统事务，并使系统接口能够立即察觉整个队列是否已满。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式