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31. 发明申请

US20060121665A1 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 有权
标题翻译：在CMOS技术中形成自对准双重杀菌剂的方法
公开(公告)号：US20060121665A1
公开(公告)日：2006-06-08
申请号：US11254934
申请日：2005-10-20
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

32. 发明申请

US20060060935A1 ISOLATION STRUCTURES IN SEMICONDUCTOR INTEGRATED CIRCUITS (IC) 失效
标题翻译：半导体集成电路中的隔离结构（IC）
公开(公告)号：US20060060935A1
公开(公告)日：2006-03-23
申请号：US10711425
申请日：2004-09-17
申请人： Brent Anderson , John Ellis-Monaghan
发明人： Brent Anderson , John Ellis-Monaghan
IPC分类号： H01L29/76
CPC分类号： H01L21/76224
摘要： A novel isolation structure in semiconductor integrated circuits (IC) and the fabrication method of the same. The isolation structure comprises (a) semiconductor a substrate, and (b) an electric isolation region embedded in and at top of the semiconductor substrate, wherein the electric isolation region comprises (i) a bubble-implanted semiconductor region and (ii) an electrically insulating cap region on top of the bubble-implanted semiconductor region.
摘要翻译：半导体集成电路（IC）中的新型隔离结构及其制造方法。隔离结构包括（a）衬底半导体，和（b）嵌入在半导体衬底中和顶部的电隔离区，其中电隔离区包括（i）注入气泡的半导体区和（ii）电在气泡注入半导体区域顶部的绝缘帽区域。

33. 发明申请

US20050164444A1 SELECTIVE NITRIDATION OF GATE OXIDES 有权
标题翻译：选择性硝化氮氧化物
公开(公告)号：US20050164444A1
公开(公告)日：2005-07-28
申请号：US10707897
申请日：2004-01-22
申请人： Jay Burnham , John Ellis-Monaghan , James Nakos , James Quinlivan
发明人： Jay Burnham , John Ellis-Monaghan , James Nakos , James Quinlivan
IPC分类号： H01L27/092 , H01L21/318 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823857
摘要： A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.
摘要翻译：半导体结构包括已经选择性地富氮的薄栅极电介质。引入的氮气量足以减少或防止栅极泄漏和掺杂剂渗透，而不会明显降低器件性能。较低浓度的氮被引入到pFET栅极电介质中，而不是nFET栅极电介质。氮化可以通过各种技术选择性地完成，包括快速热氮化（RTN），炉氮化，远程等离子体氮化（RPN），去耦等离子体氮化（DPN），阱注入和/或多晶硅注入。

34. 发明授权

US07977714B2 Wrapped gate junction field effect transistor 有权
标题翻译：封装栅结场效应晶体管
公开(公告)号：US07977714B2
公开(公告)日：2011-07-12
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

35. 发明授权

US07888156B2 Predoped transfer gate for a CMOS image sensor 有权
标题翻译： CMOS图像传感器的预置传输门
公开(公告)号：US07888156B2
公开(公告)日：2011-02-15
申请号：US11864713
申请日：2007-09-28
申请人： John Ellis-Monaghan , Jeffrey B. Johnson , Alain Loiseau
发明人： John Ellis-Monaghan , Jeffrey B. Johnson , Alain Loiseau
IPC分类号： H01L31/068
CPC分类号： H01L27/14601 , H01L27/14612 , H01L27/14689
摘要： A novel CMOS image sensor Active Pixel Sensor (APS) cell structure and method of manufacture. Particularly, a CMOS image sensor APS cell having a predoped transfer gate is formed that avoids the variations of Vt as a result of subsequent manufacturing steps. According to the preferred embodiment of the invention, the CMOS image sensor APS cell structure includes a doped p-type pinning layer and an n-type doped gate. There is additionally provided a method of forming the CMOS image sensor APS cell having a predoped transfer gate and a doped pinning layer. The predoped transfer gate prevents part of the gate from becoming p-type doped.
摘要翻译：一种新颖的CMOS图像传感器有源像素传感器（APS）单元结构及其制造方法。特别地，形成具有预制传输门的CMOS图像传感器APS单元，其避免了作为后续制造步骤的结果的Vt的变化。根据本发明的优选实施例，CMOS图像传感器APS单元结构包括掺杂的p型钉扎层和n型掺杂栅极。还提供了一种形成具有预制传输栅极和掺杂钉扎层的CMOS图像传感器APS单元的方法。预制传输门防止栅极的一部分变成p型掺杂。

36. 发明申请

US20090101941A1 WRAPPED GATE JUNCTION FIELD EFFECT TRANSISTOR 有权
标题翻译：封装栅极连接场效应晶体管
公开(公告)号：US20090101941A1
公开(公告)日：2009-04-23
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

37. 发明申请

US20070184614A1 RECESSED GATE FOR A CMOS IMAGE SENSOR 有权
标题翻译： CMOS图像传感器的接收门
公开(公告)号：US20070184614A1
公开(公告)日：2007-08-09
申请号：US11735223
申请日：2007-04-13
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
IPC分类号： H01L21/336
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.
摘要翻译：一种新颖的CMOS图像传感器单元结构及其制造方法。成像传感器包括具有上表面的基板，包括形成在基板上的电介质层的栅极和形成在栅极电介质层上的栅极导体，形成在基板表面附近的第一导电类型的集合阱层栅极导体的第一侧，形成在基板表面上的集电阱顶部的第二导电类型的钉扎层，以及邻近栅极导体的第二侧形成的第一导电类型的扩散区域，栅极导体形成沟道收集阱层和扩散区域之间的区域。栅极导体的底部的一部分在衬底的表面下方凹进。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到深度，使得收集阱与沟道区相交，从而消除由钉扎层引起的任何潜在的屏障干扰。

38. 发明申请

US20070102740A1 DEEP TRENCH CONTACT AND ISOLATION OF BURIED PHOTODETECTORS 失效
标题翻译： DEEP TRENCH接触和分离的BEDIED光电子
公开(公告)号：US20070102740A1
公开(公告)日：2007-05-10
申请号：US11164098
申请日：2005-11-10
申请人： John Ellis-Monaghan , Jeffrey Gambino , Jeffrey Johnson , Jerome Lasky
发明人： John Ellis-Monaghan , Jeffrey Gambino , Jeffrey Johnson , Jerome Lasky
IPC分类号： H01L31/113
CPC分类号： H01L27/14647 , H01L27/14603 , H01L27/14634
摘要： The invention provides vertically-stacked photodiodes buried in a semiconductor material that are isolated and selectively contacted by deep trenches. One embodiment of the invention provides a pixel sensor comprising: a plurality of photosensitive elements formed in a substrate, each photosensitive element being adapted to generate photocharges in response to electromagnetic radiation; and a plurality of photocharge transfer devices, each photocharge transfer device being coupled to at least one of the plurality of photosensitive elements.
摘要翻译：本发明提供了埋藏在半导体材料中的垂直堆叠的光电二极管，其被深沟槽隔离并选择性地接触。本发明的一个实施例提供了一种像素传感器，包括：形成在基板中的多个感光元件，每个光敏元件适于响应于电磁辐射产生光电荷; 以及多个光电荷转移装置，每个光电荷转移装置耦合到所述多个感光元件中的至少一个。

39. 发明申请

US20070023796A1 PINNING LAYER FOR PIXEL SENSOR CELL AND METHOD THEREOF 审中-公开
标题翻译：用于像素传感器单元的密封层及其方法
公开(公告)号：US20070023796A1
公开(公告)日：2007-02-01
申请号：US11161224
申请日：2005-07-27
申请人： James Adkisson , John Ellis-Monaghan
发明人： James Adkisson , John Ellis-Monaghan
IPC分类号： H01L31/113 , H01L31/062
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/1463
摘要： A novel pixel sensor cell structure and method of manufacture. The pixel sensor cell includes a collection well region of a first conductivity type and a pinning layer formed in a substrate. The pinning layer includes a first impurity region of a second conductivity type and a second impurity region of the second conductivity type. The first and second impurity regions can be independently formed to affect multiple parameters of the pixel sensor cell.
摘要翻译：一种新颖的像素传感器单元结构及其制造方法。像素传感器单元包括第一导电类型的收集阱区域和形成在衬底中的钉扎层。钉扎层包括第二导电类型的第一杂质区和第二导电类型的第二杂质区。可以独立地形成第一和第二杂质区域以影响像素传感器单元的多个参数。

40. 发明申请

US20060192233A1 BODY POTENTIAL IMAGER CELL 有权
标题翻译：身体潜像成像细胞
公开(公告)号：US20060192233A1
公开(公告)日：2006-08-31
申请号：US10906625
申请日：2005-02-28
申请人： John Ellis-Monaghan , Mark Jaffe , Alain Loiseau
发明人： John Ellis-Monaghan , Mark Jaffe , Alain Loiseau
IPC分类号： H01L27/148
CPC分类号： H01L27/14643 , H01L27/14603 , H01L27/14609 , H01L27/14679
摘要： An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.
摘要翻译：成像电路，成像传感器和成像方法。所述成像单元电路包括一个或多个成像单元电路，每个成像单元电路包括：晶体管，具有浮动体，用于响应于浮体暴露于电磁辐射而保持在浮体中产生的电荷; 用于偏置晶体管的装置，其中晶体管的输出响应于电磁辐射; 以及用于选择性地将浮动体连接到复位电压源的装置。

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