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1. 发明申请

US20070145438A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20070145438A1
公开(公告)日：2007-06-28
申请号：US11681454
申请日：2007-03-02
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

2. 发明申请

US20060226456A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20060226456A1
公开(公告)日：2006-10-12
申请号：US10907570
申请日：2005-04-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

3. 发明申请

US20070184614A1 RECESSED GATE FOR A CMOS IMAGE SENSOR 有权
标题翻译： CMOS图像传感器的接收门
公开(公告)号：US20070184614A1
公开(公告)日：2007-08-09
申请号：US11735223
申请日：2007-04-13
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
IPC分类号： H01L21/336
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.
摘要翻译：一种新颖的CMOS图像传感器单元结构及其制造方法。成像传感器包括具有上表面的基板，包括形成在基板上的电介质层的栅极和形成在栅极电介质层上的栅极导体，形成在基板表面附近的第一导电类型的集合阱层栅极导体的第一侧，形成在基板表面上的集电阱顶部的第二导电类型的钉扎层，以及邻近栅极导体的第二侧形成的第一导电类型的扩散区域，栅极导体形成沟道收集阱层和扩散区域之间的区域。栅极导体的底部的一部分在衬底的表面下方凹进。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到深度，使得收集阱与沟道区相交，从而消除由钉扎层引起的任何潜在的屏障干扰。

4. 发明申请

US20060124976A1 RECESSED GATE FOR AN IMAGE SENSOR 有权
标题翻译：图像传感器的门
公开(公告)号：US20060124976A1
公开(公告)日：2006-06-15
申请号：US10905097
申请日：2004-12-15
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
IPC分类号： H01L31/113 , H01L29/76 , H01L29/94
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.
摘要翻译：一种新颖的图像传感器单元结构及其制造方法。成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区。栅极导体底部的一部分凹陷在基板的表面下方。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

5. 发明申请

US20070158711A1 CMOS SENSORS HAVING CHARGE PUSHING REGIONS 失效
标题翻译：具有充电推动区域的CMOS传感器
公开(公告)号：US20070158711A1
公开(公告)日：2007-07-12
申请号：US11275497
申请日：2006-01-10
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Jeffrey Johnson , Jerome Lasky , Richard Rassel
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Jeffrey Johnson , Jerome Lasky , Richard Rassel
IPC分类号： H01L31/113 , H01L27/148 , H01L29/768
CPC分类号： H01L27/1462 , H01L27/14603 , H01L27/1463
摘要： Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.
摘要翻译：结构及其形成方法。该半导体结构包括包含第一半导体区域和第二半导体区域的光电二极管。第一和第二半导体区域分别掺杂有第一和第二掺杂极性，并且第一和第二掺杂极性相反。半导体结构还包括传输门，其包括（i）第一延伸区，（ii）第二延伸区和（iii）浮动扩散区。第一和第二延伸区分别与光电二极管和浮动扩散区直接物理接触。半导体结构还包括电荷推送区域。电荷推送区域与第一半导体区域重叠，并且不与浮动扩散区域重叠。电荷推送区域包括透明且导电的材料。

6. 发明申请

US20070102740A1 DEEP TRENCH CONTACT AND ISOLATION OF BURIED PHOTODETECTORS 失效
标题翻译： DEEP TRENCH接触和分离的BEDIED光电子
公开(公告)号：US20070102740A1
公开(公告)日：2007-05-10
申请号：US11164098
申请日：2005-11-10
申请人： John Ellis-Monaghan , Jeffrey Gambino , Jeffrey Johnson , Jerome Lasky
发明人： John Ellis-Monaghan , Jeffrey Gambino , Jeffrey Johnson , Jerome Lasky
IPC分类号： H01L31/113
CPC分类号： H01L27/14647 , H01L27/14603 , H01L27/14634
摘要： The invention provides vertically-stacked photodiodes buried in a semiconductor material that are isolated and selectively contacted by deep trenches. One embodiment of the invention provides a pixel sensor comprising: a plurality of photosensitive elements formed in a substrate, each photosensitive element being adapted to generate photocharges in response to electromagnetic radiation; and a plurality of photocharge transfer devices, each photocharge transfer device being coupled to at least one of the plurality of photosensitive elements.
摘要翻译：本发明提供了埋藏在半导体材料中的垂直堆叠的光电二极管，其被深沟槽隔离并选择性地接触。本发明的一个实施例提供了一种像素传感器，包括：形成在基板中的多个感光元件，每个光敏元件适于响应于电磁辐射产生光电荷; 以及多个光电荷转移装置，每个光电荷转移装置耦合到所述多个感光元件中的至少一个。

7. 发明申请

US20070051948A1 TEST STRUCTURE AND METHOD FOR DETECTING AND STUDYING CRYSTAL LATTICE DISLOCATION DEFECTS IN INTEGRATED CIRCUIT DEVICES 失效
标题翻译：用于检测和研究集成电路设备中的晶体尺寸分离缺陷的测试结构和方法
公开(公告)号：US20070051948A1
公开(公告)日：2007-03-08
申请号：US11162128
申请日：2005-08-30
申请人： Jonathan Fales , Jerome Lasky
发明人： Jonathan Fales , Jerome Lasky
IPC分类号： H01L23/58
CPC分类号： H01L22/32
摘要： A test structure (200, 200′) having an array (224) of test devices (220) for detecting and studying defects that can occur in an integrated circuit device, e.g., a transistor (144), due to the relative positioning of one component (100) of the device with respect to another component (108) of the device. The test devices in the array are of a like kind, but vary in their configuration. The differences in the configurations are predetermined and selected with the intent of forcing defects to occur within at least some of the test devices. During testing, the responses of the test devices are sensed so as to determine whether or not a defect has occurred in any one or more of the test devices. If a defective test device is detected, the corresponding wafer (204) may be subjected to physical failure analysis for yield learning.
摘要翻译：一种测试结构（200,200'），具有用于检测和研究集成电路器件例如晶体管（144）中可能发生的缺陷的测试器件（220）的阵列（224），由于一个相对于设备的另一组件（108）的设备的组件（100）。阵列中的测试设备是类似的，但是它们的配置是不同的。配置中的差异是预先确定的，其目的是强制在至少一些测试设备内发生缺陷。在测试期间，感测测试装置的响应，以便确定在任何一个或多个测试装置中是否发生了缺陷。如果检测到有缺陷的测试装置，则可以对相应的晶片（204）进行用于产量学习的物理故障分析。

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