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1. 发明申请

US20050164444A1 SELECTIVE NITRIDATION OF GATE OXIDES 有权
标题翻译：选择性硝化氮氧化物
公开(公告)号：US20050164444A1
公开(公告)日：2005-07-28
申请号：US10707897
申请日：2004-01-22
申请人： Jay Burnham , John Ellis-Monaghan , James Nakos , James Quinlivan
发明人： Jay Burnham , John Ellis-Monaghan , James Nakos , James Quinlivan
IPC分类号： H01L27/092 , H01L21/318 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823857
摘要： A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.
摘要翻译：半导体结构包括已经选择性地富氮的薄栅极电介质。引入的氮气量足以减少或防止栅极泄漏和掺杂剂渗透，而不会明显降低器件性能。较低浓度的氮被引入到pFET栅极电介质中，而不是nFET栅极电介质。氮化可以通过各种技术选择性地完成，包括快速热氮化（RTN），炉氮化，远程等离子体氮化（RPN），去耦等离子体氮化（DPN），阱注入和/或多晶硅注入。

2. 发明申请

US20050040480A1 Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors 有权
标题翻译：热氮分配方法提高高掺杂超薄栅极电容器的均匀性
公开(公告)号：US20050040480A1
公开(公告)日：2005-02-24
申请号：US10652307
申请日：2003-09-02
申请人： Jay Burnham , James Nakos , James Quinlivan , Steven Shank , Deborah Tucker , Beth Ward
发明人： Jay Burnham , James Nakos , James Quinlivan , Steven Shank , Deborah Tucker , Beth Ward
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L29/51 , H01L29/76
CPC分类号： H01L21/28202 , H01L21/28185 , H01L21/28211 , H01L21/3144 , H01L21/31612 , H01L21/3185 , H01L29/513 , H01L29/518
摘要： Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.
摘要翻译：使用诸如远程等离子体氮化（RPN）的方法将氮气引入栅极介电层。然而，这些方法产生氮化层，其中层的横截面轮廓和氮分布都不均匀。使氮化层进行额外的NO退火工艺增加了氮化层的均匀性。

3. 发明申请

US20050048705A1 METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC 有权
标题翻译：氮化硅氧化物电介质的制备方法
公开(公告)号：US20050048705A1
公开(公告)日：2005-03-03
申请号：US10604905
申请日：2003-08-26
申请人： Jay Burnham , James Nakos , James Quinlivan , Bernie Roque , Steven Shank , Beth Ward
发明人： Jay Burnham , James Nakos , James Quinlivan , Bernie Roque , Steven Shank , Beth Ward
IPC分类号： H01L20060101 , H01L21/31 , H01L21/336 , H01L21/469
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/3144 , H01L29/518
摘要： A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.
摘要翻译：一种制造栅极电介质层的方法，包括：提供衬底; 在所述基板的顶表面上形成二氧化硅层; 在还原气氛中进行等离子体氮化，将二氧化硅层转换成氮氧化硅层。如此形成的电介质层可用于制造MOSFET。

4. 发明申请

US20080014692A1 METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC 有权
标题翻译：氮化硅氧化物电介质的制备方法
公开(公告)号：US20080014692A1
公开(公告)日：2008-01-17
申请号：US11778238
申请日：2007-07-16
申请人： Jay Burnham , James Nakos , James Quinlivan , Bernie Roque , Steven Shank , Beth Ward
发明人： Jay Burnham , James Nakos , James Quinlivan , Bernie Roque , Steven Shank , Beth Ward
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/3144 , H01L29/518
摘要： A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.
摘要翻译：一种制造栅极电介质层的方法。该方法包括：提供衬底; 在所述基板的顶表面上形成二氧化硅层; 在还原气氛中进行等离子体氮化，将二氧化硅层转换成氮氧化硅层。如此形成的电介质层可用于制造MOSFET。

5. 发明申请

US20050112888A1 Semiconductor metal contamination reduction for ultra-thin gate dielectrics 失效
标题翻译：用于超薄栅极电介质的半导体金属污染减少
公开(公告)号：US20050112888A1
公开(公告)日：2005-05-26
申请号：US10981232
申请日：2004-11-04
申请人： Jay Burnham , James Elliott , Kenneth Gault , Mousa Ishaq , Steven Shank , Mary St. Lawrence
发明人： Jay Burnham , James Elliott , Kenneth Gault , Mousa Ishaq , Steven Shank , Mary St. Lawrence
IPC分类号： H01L21/28 , H01L21/306 , H01L21/8238 , H01L29/51 , H01L21/302 , H01L21/461
CPC分类号： H01L21/28194 , H01L21/02046 , H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , Y10S257/913
摘要： A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.
摘要翻译：提供了用于大大减少或消除随后的多晶硅沉积期间形成的金属污染物的双层电介质结构。双层电介质结构包括位于底表面区域顶部富含氯的上表面区域。富含氯的上表面区域除去在随后形成多晶硅层期间存在于结构顶部的金属污染物。还提供了形成双层结构的方法。

6. 发明授权

US5947053A Wear-through detector for multilayered parts and methods of using same 失效
标题翻译：用于多层零件的磨损检测器及其使用方法
公开(公告)号：US5947053A
公开(公告)日：1999-09-07
申请号：US5634
申请日：1998-01-09
申请人： Jay Burnham , Harold G. Linde , Nicholas N. Mone, Jr. , Ronald A. Warren
发明人： Jay Burnham , Harold G. Linde , Nicholas N. Mone, Jr. , Ronald A. Warren
IPC分类号： G01N17/00 , G01B15/00 , G01B21/08 , G21K5/04 , G21K5/08
CPC分类号： G01N17/00 , H01J2237/30466 , H01J2237/31701
摘要： The present invention relates to wear-through detection in multilayered parts. This invention specifically encompasses, in one aspect, wear-through detection in semiconductor vacuum processing systems in which a wear indicator that will release a detectable constituent upon exposure to processing conditions is used inside the semiconductor vacuum processing tool. This invention permits real time detection of wear during operation of semiconductor vacuum processing equipment.
摘要翻译：本发明涉及多层部件中的磨损检测。本发明在一个方面具体包括半导体真空处理系统中的穿透检测，其中在半导体真空处理工具内部使用将在暴露于加工条件时释放可检测成分的磨损指示器。本发明允许在半导体真空处理设备的操作期间实时检测磨损。

7. 发明授权

US06770501B2 Deuterium reservoirs and ingress paths 失效
标题翻译：氘池和入口路径
公开(公告)号：US06770501B2
公开(公告)日：2004-08-03
申请号：US10277835
申请日：2002-10-23
申请人： Jay Burnham , Eduard A. Cartier , Thomas G. Ference , Steven W. Mittl , Anthony K. Stamper
发明人： Jay Burnham , Eduard A. Cartier , Thomas G. Ference , Steven W. Mittl , Anthony K. Stamper
IPC分类号： H01L213205
CPC分类号： H01L21/76224 , H01L21/3003 , H01L21/823481
摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.
摘要翻译：半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。

8. 发明授权

US06521977B1 Deuterium reservoirs and ingress paths 有权
标题翻译：氘池和入口路径
公开(公告)号：US06521977B1
公开(公告)日：2003-02-18
申请号：US09489277
申请日：2000-01-21
申请人： Jay Burnham , Eduard A. Cartier , Thomas G. Ference , Steven W. Mittl , Anthony K. Stamper
发明人： Jay Burnham , Eduard A. Cartier , Thomas G. Ference , Steven W. Mittl , Anthony K. Stamper
IPC分类号： H01L2358
CPC分类号： H01L21/76224 , H01L21/3003 , H01L21/823481
摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.
摘要翻译：半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。

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