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31. 发明申请

US20070262305A1 INTEGRATED CIRCUIT PROTECTION FROM ESD DAMAGE DURING FABRICATION 审中-公开
标题翻译：集成电路在制造过程中受到ESD损害的保护
公开(公告)号：US20070262305A1
公开(公告)日：2007-11-15
申请号：US11382492
申请日：2006-05-10
申请人： James Adkisson , Jeffrey Gambino , Richard Rassel , Steven Voldman
发明人： James Adkisson , Jeffrey Gambino , Richard Rassel , Steven Voldman
IPC分类号： H01L23/58
CPC分类号： H01L23/60 , H01L22/32 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit wafer containing a plurality of integrated circuit chips and having a common substrate, each chip formed with an internal region in the interior of the chip and a removable external region on the perimeter of the internal region and circuitry disposed preferably in the external region and connected to at least one pad of an integrated circuit chip and the wafer substrate to establish electrical connection during electrostatic discharge and prevent ESD damage. The pad and substrate are isolated during tested of the integrated circuit chips in the wafer. Preferably, the external region is removed when the integrated circuit chips are diced from the wafer.
摘要翻译：一种包含多个集成电路芯片并具有公共基板的半导体集成电路晶片，每个芯片在芯片的内部形成有内部区域，并且在内部区域的周边上具有可移除的外部区域，优选地设置在外部并且连接到集成电路芯片的至少一个焊盘和晶片衬底，以在静电放电期间建立电连接并防止ESD损坏。在晶片中的集成电路芯片的测试期间隔离衬垫和衬底。优选地，当从晶片切割集成电路芯片时，去除外部区域。

32. 发明申请

US20070184614A1 RECESSED GATE FOR A CMOS IMAGE SENSOR 有权
标题翻译： CMOS图像传感器的接收门
公开(公告)号：US20070184614A1
公开(公告)日：2007-08-09
申请号：US11735223
申请日：2007-04-13
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
IPC分类号： H01L21/336
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.
摘要翻译：一种新颖的CMOS图像传感器单元结构及其制造方法。成像传感器包括具有上表面的基板，包括形成在基板上的电介质层的栅极和形成在栅极电介质层上的栅极导体，形成在基板表面附近的第一导电类型的集合阱层栅极导体的第一侧，形成在基板表面上的集电阱顶部的第二导电类型的钉扎层，以及邻近栅极导体的第二侧形成的第一导电类型的扩散区域，栅极导体形成沟道收集阱层和扩散区域之间的区域。栅极导体的底部的一部分在衬底的表面下方凹进。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到深度，使得收集阱与沟道区相交，从而消除由钉扎层引起的任何潜在的屏障干扰。

33. 发明申请

US20070164337A1 FLIP FERAM CELL AND METHOD TO FORM SAME 有权
标题翻译：翻转毛细胞及其形成方法
公开(公告)号：US20070164337A1
公开(公告)日：2007-07-19
申请号：US11687000
申请日：2007-03-16
申请人： James Adkisson , Charles Black , Alfred Grill , Randy Mann , Deborah Neumayer , Wilbur Pricer , Katherine Saenger , Thomas Shaw
发明人： James Adkisson , Charles Black , Alfred Grill , Randy Mann , Deborah Neumayer , Wilbur Pricer , Katherine Saenger , Thomas Shaw
IPC分类号： H01L29/94
CPC分类号： H01L28/55 , H01L27/0629 , H01L27/11502 , H01L27/11507 , Y10S438/977
摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
摘要翻译：提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。本发明的方法包括分别形成CMOS结构和铁电输送晶片。然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

34. 发明申请

US20070158711A1 CMOS SENSORS HAVING CHARGE PUSHING REGIONS 失效
标题翻译：具有充电推动区域的CMOS传感器
公开(公告)号：US20070158711A1
公开(公告)日：2007-07-12
申请号：US11275497
申请日：2006-01-10
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Jeffrey Johnson , Jerome Lasky , Richard Rassel
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Jeffrey Johnson , Jerome Lasky , Richard Rassel
IPC分类号： H01L31/113 , H01L27/148 , H01L29/768
CPC分类号： H01L27/1462 , H01L27/14603 , H01L27/1463
摘要： Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.
摘要翻译：结构及其形成方法。该半导体结构包括包含第一半导体区域和第二半导体区域的光电二极管。第一和第二半导体区域分别掺杂有第一和第二掺杂极性，并且第一和第二掺杂极性相反。半导体结构还包括传输门，其包括（i）第一延伸区，（ii）第二延伸区和（iii）浮动扩散区。第一和第二延伸区分别与光电二极管和浮动扩散区直接物理接触。半导体结构还包括电荷推送区域。电荷推送区域与第一半导体区域重叠，并且不与浮动扩散区域重叠。电荷推送区域包括透明且导电的材料。

35. 发明申请

US20070087463A1 PIXEL SENSOR HAVING DOPED ISOLATION STRUCTURE SIDEWALL 有权
标题翻译：具有分离隔离结构的PIXEL传感器
公开(公告)号：US20070087463A1
公开(公告)日：2007-04-19
申请号：US11563531
申请日：2006-11-27
申请人： James Adkisson , Mark Jaffe , Robert Leidy
发明人： James Adkisson , Mark Jaffe , Robert Leidy
IPC分类号： H01L21/00
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffiusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a comer, or a comer portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离结构。沟槽隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散过程，由此在退火期间，存在于沿着沟槽中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。可替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其拐角部分来减小其尺寸来执行。

36. 发明申请

US20070023796A1 PINNING LAYER FOR PIXEL SENSOR CELL AND METHOD THEREOF 审中-公开
标题翻译：用于像素传感器单元的密封层及其方法
公开(公告)号：US20070023796A1
公开(公告)日：2007-02-01
申请号：US11161224
申请日：2005-07-27
申请人： James Adkisson , John Ellis-Monaghan
发明人： James Adkisson , John Ellis-Monaghan
IPC分类号： H01L31/113 , H01L31/062
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/1463
摘要： A novel pixel sensor cell structure and method of manufacture. The pixel sensor cell includes a collection well region of a first conductivity type and a pinning layer formed in a substrate. The pinning layer includes a first impurity region of a second conductivity type and a second impurity region of the second conductivity type. The first and second impurity regions can be independently formed to affect multiple parameters of the pixel sensor cell.
摘要翻译：一种新颖的像素传感器单元结构及其制造方法。像素传感器单元包括第一导电类型的收集阱区域和形成在衬底中的钉扎层。钉扎层包括第二导电类型的第一杂质区和第二导电类型的第二杂质区。可以独立地形成第一和第二杂质区域以影响像素传感器单元的多个参数。

37. 发明申请

US20060124976A1 RECESSED GATE FOR AN IMAGE SENSOR 有权
标题翻译：图像传感器的门
公开(公告)号：US20060124976A1
公开(公告)日：2006-06-15
申请号：US10905097
申请日：2004-12-15
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Jerome Lasky
IPC分类号： H01L31/113 , H01L29/76 , H01L29/94
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.
摘要翻译：一种新颖的图像传感器单元结构及其制造方法。成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区。栅极导体底部的一部分凹陷在基板的表面下方。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

38. 发明申请

US20060073689A1 METHOD FOR FABRICATING DOPED POLYSILICON LINES 有权
标题翻译：用于制造掺杂多晶硅线的方法
公开(公告)号：US20060073689A1
公开(公告)日：2006-04-06
申请号：US10711771
申请日：2004-10-04
申请人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
发明人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
IPC分类号： H01L21/3205
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

39. 发明申请

US20070287275A1 METHOD FOR FABRICATING DOPED POLYSILICON LINES 审中-公开
标题翻译：用于制造掺杂多晶硅线的方法
公开(公告)号：US20070287275A1
公开(公告)日：2007-12-13
申请号：US11835745
申请日：2007-08-08
申请人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
发明人： James Adkisson , John Ellis-Monaghan , Glenn MacDougall , Dale Martin , Kirk Peterson , Bruce Porth
IPC分类号： H01L21/425
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：在衬底的顶表面上形成电介质层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，N掺杂物质基本上包含在多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

40. 发明申请

US20070127172A1 ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING 失效
标题翻译：使用光电传感器的需求电路功能执行
公开(公告)号：US20070127172A1
公开(公告)日：2007-06-07
申请号：US11275058
申请日：2005-12-06
申请人： Wagdi Abadeer , James Adkisson , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Michael Hauser , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , James Adkisson , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Michael Hauser , Jed Rankin , William Tonti
IPC分类号： H02H9/00
CPC分类号： H01L23/5256 , H01L23/525 , H01L27/14609 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.
摘要翻译：公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。一旦封装的芯片放置在系统中，也可以将ESD保护装置从输入焊盘断开。不需要额外的引脚。

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